SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

• US 20170338239A1
• Filed: 05/23/2016
• Published: 11/23/2017
• Est. Priority Date: 05/23/2016
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liu, Wei-Chang, Chen, Zhen, Wang, Shen-De, Ta, Wei, Xiang, Wang, Chiu, Yi-Shan
• Application Number:
  US15/161,419
• Publication Number:
  US 20170338239A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. The gate structures are spaced from each other by a spacing S. Each gate structure includes a dielectric layer and a gate electrode. The dielectric layer has an U-shape and defines an opening toward upside. The gate electrode is disposed in the opening. Each gate structure has a length L. A ratio of S/L is smaller than 1.

Claims

1. A semiconductor structure, comprising:

a substrate; and

a plurality of memory cells disposed on the substrate, each of the memory cells comprising a gate structure, wherein the gate structures are spaced from each other by a spacing S, and each of the gate structures comprising;

a dielectric layer having an U-shape and defining an opening toward upside; and

a gate electrode disposed in the opening;

wherein each of the gate structures has a length L, and a ratio of S/L is smaller than 1, and wherein the spacing S is smaller than 20 nm.

2. The semiconductor structure according to claim 1, wherein the memory cells are NAND flash cells.

3. The semiconductor structure according to claim 1, wherein the memory cells constitute a string.

4. The semiconductor structure according to claim 1, wherein the dielectric layer is a memory layer.

5. The semiconductor structure according to claim 1, wherein the dielectric layer has an ONO or ONONO structure.

6. The semiconductor structure according to claim 1, wherein the ratio of S/L substantially equals to 1/2.

7. The semiconductor structure according to claim 1, wherein each of the memory cells further comprises two doped regions disposed in the substrate at two sides of the gate electrode, respectively.

8. A method for manufacturing a semiconductor structure, comprising:

forming a plurality of hard mask features on a substrate by sidewall image transfer (SIT) technique, the hard mask features spaced from each other;

forming a dielectric layer conformally covering the hard mask features, the dielectric layer defining a plurality of open spaces;

filling a conductive material into the open spaces;

removing the hard mask features and portions of the dielectric layer formed thereon, so as to form a plurality of gate structures respectively for a plurality of memory cells, wherein the gate structures are spaced from each other by a spacing S, and for each of the gate structures, the dielectric layer has an U-shape and defines an opening toward upside, the conductive material constitute a gate electrode disposed in the opening, the gate structure has a length L, and a ratio of S/L is smaller than 1.

9. The method according to claim 8, wherein forming the hard mask features comprises:

forming a hard mask layer on the substrate;

forming an intermediate layer on the hard mask layer;

forming a plurality of place holders on the intermediate layer;

forming a spacer layer conformally covering the place holders;

removing the place holders and portions of the spacer layer formed thereon, so as to form a plurality of spacers on the intermediate layer; and

transferring a pattern of the spacers to the hard mask layer.

10. The method according to claim 9, wherein the hard mask layer is formed of SiN.

11. The method according to claim 8, further comprising:

before forming the dielectric layer, forming liners on sidewalls of the hard mask features;

wherein the liners are removed at a same step of removing the hard mask features.

12. The method according to claim 8, wherein removing the hard mask features and the portions of the dielectric layer formed thereon comprises a planarization step and an etching step.

13. The method according to claim 12, wherein the etching step using H₃PO₄ as an etchant.

14. The method according to claim 8, wherein the memory cells are NAND flash cells.

15. The method according to claim 8, wherein the memory cells constitute a string.

16. The method according to claim 8, wherein the dielectric layer is a memory layer.

17. The method according to claim 8, wherein the dielectric layer has an ONO or ONONO structure.

18. The method according to claim 8, wherein the ratio of S/L substantially equals to 1/2.

19. The method according to claim 8, further comprising:

forming doped regions in the substrate between the gate structures.