SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20170338241A1
• Filed: 09/29/2016
• Published: 11/23/2017
• Est. Priority Date: 05/23/2016
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Nam Jae
• Granted Patent: US 9,985,048 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor device includes a first structure, a dummy buffer stack structure, a peripheral contact hole, and a peripheral contact plug. The first structure may include a substrate and a peripheral circuit disposed on the substrate. The dummy buffer stack structure may be disposed on the first structure. The dummy buffer stack structure may include dummy interlayer insulating layers and dummy sacrificial insulating layers, which are alternately stacked, and first dummy conductive rings stacked in a line inside the respective dummy sacrificial insulating layers. The peripheral contact hole may penetrate the dummy buffer stack structure. The peripheral contact hole may be surrounded by the first dummy conductive rings. The peripheral contact plug may be disposed in the peripheral contact hole. The peripheral contact plug may extend to be connected to the peripheral circuit.

Claims

1. A semiconductor device comprising:

a first structure including a substrate and a peripheral circuit disposed on the substrate;

a dummy buffer stack structure disposed on the first structure, the dummy buffer stack structure including dummy interlayer insulating layers and dummy sacrificial insulating layers, which are alternately stacked, and first dummy conductive rings stacked in a line inside the respective dummy sacrificial insulating layers;

a peripheral contact hole penetrating the dummy buffer stack structure, the peripheral contact hole being surrounded by the first dummy conductive rings; and

a peripheral contact plug disposed in the peripheral contact hole, the peripheral contact plug extending to be connected to the peripheral circuit.

2. The semiconductor device of claim 1, further comprising:

a dummy source stack structure disposed between the first structure and the dummy buffer stack structure; and

a source penetrating insulating layer penetrating the dummy source stack structure disposed under the peripheral contact hole, the peripheral contact plug penetrating the source penetrating insulating layer.

3. The semiconductor device of claim 2, wherein the dummy source stack structure includes:

a first source conductive layer;

a protective layer formed on the first source conductive layer; and

a source sacrificial layer formed on the protective layer.

4. The semiconductor device of claim 2, further comprising:

an etch stop pattern disposed between the dummy source stack structure and the dummy buffer stack structure; and

a second dummy conductive ring disposed at the same level as the etch stop pattern, the second dummy conductive ring overlapping, at least in part, the first dummy conductive rings.

5. The semiconductor device of claim 1, wherein the peripheral circuit includes a resistor electrically connected to the peripheral contact plug.

6. The semiconductor device of claim 1, wherein the peripheral circuit includes a driver transistor electrically connected to the peripheral contact plug via a connecting structure.

7. The semiconductor device of claim 1, further comprising:

a cell stack structure disposed at the same height as the dummy buffer stack structure on the first structure, the cell stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked, and cell pillars penetrating the interlayer insulating layers and the conductive patterns; and

a source stack structure disposed between the first structure and the cell stack structure, the cell pillar penetrating a portion of the source stack structure.

8. The semiconductor device of claim 7, wherein the source stack structure includes:

a first source conductive layer; and

a second source conductive layer disposed on the first source conductive layer and penetrated by the cell pillar, the second source conductive layer contacting a channel layer of the cell pillar.

9. The semiconductor device of claim 8, wherein the cell pillar includes:

the channel layer penetrating the interlayer insulating layers, the conductive patterns and the second source conductive layer, the channel layer extending inside the first source conductive layer;

a first memory pattern disposed between the channel layer and the interlayer insulating layers and conductive patterns; and

a second memory pattern isolated from the first memory pattern by the second source conductive layer, the second memory pattern being disposed between the channel layer and the first source conductive layer.

10. The semiconductor device of claim 7, wherein the peripheral contact hole has a wider diameter than the cell pillar.

11. A semiconductor device comprising:

a first structure including a substrate and a peripheral circuit disposed on the substrate;

a second structure disposed on the first structure, the second structure including a source stack structure and a dummy source stack structure, which are disposed at the same height and formed into different stack structures;

a third structure disposed on the second structure, the third structure including a cell stack structure and a dummy buffer stack structure, which are isolated from each other; and

a peripheral contact plug penetrating the dummy buffer stack structure and the dummy source stack structure, the peripheral contact plug being electrically connected to the peripheral circuit.

12. The semiconductor device of claim 11, wherein the peripheral circuit includes a resistor connected to the peripheral contact plug.

13. The semiconductor device of claim 11, wherein the peripheral circuit includes a driver transistor electrically connected to the peripheral contact plug via a connecting structure.

14. The semiconductor device of claim 11, wherein the source stack structure includes:

a first source conductive layer; and

a second source conductive layer disposed on the first source conductive layer.

15. The semiconductor device of claim 14, wherein the cell stack structure includes:

interlayer insulating layers and conductive patterns, which are alternately stacked on the second source conductive layer; and

a channel layer extending inside the first source conductive layer by penetrating the interlayer insulating layers, the conductive patterns, and the second source conductive layer.

16. The semiconductor device of claim 15, further comprising:

a first memory pattern disposed between the channel layer, the interlayer insulating layers, and conductive patterns while surrounding the channel layer; and

a second memory pattern isolated from the first memory pattern by the second source conductive layer, the second memory pattern being disposed between the first source conductive layer and the channel layer while surrounding the channel layer.

17. The semiconductor device of claim 11, wherein the dummy source stack structure includes:

a first source conductive layer;

a protective layer formed on the first source conductive layer; and

a source sacrificial layer formed on the protective layer.

18. The semiconductor device of claim 11, wherein the dummy buffer stack structure includes:

dummy interlayer insulating layers and dummy sacrificial insulating layers, which are alternately stacked on the dummy source stack structure; and

first dummy conductive rings stacked in a line inside the respective dummy sacrificial insulating layers, the first dummy conductive rings surrounding the peripheral contact plug.

19. The semiconductor device of claim 18, further comprising:

an etch stop pattern disposed between the dummy source stack structure and the dummy buffer stack structure; and

a second dummy conductive ring disposed at the same level as the etch stop pattern, the second dummy conductive ring overlapping, at least in part, the first dummy conductive rings.

20. The semiconductor device of claim 11, further comprising:

a source penetrating insulating layer penetrating the dummy source stack structure, the peripheral contact plug penetrating the source penetrating insulating layer;

a slit insulating layer disposed on the third structure to cover the third structure, the slit insulating layer extending to penetrate the cell stack structure and the dummy buffer stack structure, the peripheral contact plug penetrating the slit insulating layer; and

an insulating spacers disposed between a sidewall of the cell stack structure and the slit insulating layer and between a sidewall of the dummy buffer stack structure and the peripheral contact plug.