Floating Body Contact Circuit Method for Improving ESD Performance and Switching Speed
First Claim
Patent Images
1. An electronic circuit including:
- (a) at least one field effect transistor (FET), each FET including;
(1) a gate, a drain, a source, and a body;
(2) a gate resistor series connected to the gate of such FET;
(3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and
(4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and
(b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including;
(1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and
(2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal.
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Abstract
Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.
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Citations
42 Claims
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1. An electronic circuit including:
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(a) at least one field effect transistor (FET), each FET including; (1) a gate, a drain, a source, and a body; (2) a gate resistor series connected to the gate of such FET; (3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and (4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and (b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including; (1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and (2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit including:
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(a) at least two stacked field effect transistors (FET), each FET including; (1) a gate, a drain, a source, and a body; (2) a gate resistor series connected to the gate of such FET; (3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and (4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and (b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including; (1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and (2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method for improving electrostatic discharge tolerance and switching speed in an integrated circuit, including:
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(a) providing at least one field effect transistor (FET), each FET including; (1) a gate, a drain, a source, and a body; (2) a gate resistor series connected to the gate of such FET; (3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and (4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and (b) providing at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including; (1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and (2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. An integrated circuit including:
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(a) at least one field effect transistor (FET) configured to switch or process a radio frequency signal, each FET including; (1) a gate, a drain, a source, and a body; (2) a gate resistor series connected to the gate of such FET at a first node and having a second node resistively separated from the first node; (3) an accumulated charge sink (ACS) diode connected to the body of such FET; and (4) at least one ACS resistance series connected to the ACS diode, wherein the series-connected at least one ACS resistance and the ACS diode are connected to the second node, and the at least one ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS diode; and (b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including; (1) a selectable resistor coupled in series between (A) a common control terminal for at least one FET and (B) at least one second node; and (2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42)
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Specification