ULTRA LOW POWER WIDEBAND NON-COHERENT BINARY PHASE SHIFT KEYING DEMODULATOR USING FIRST ORDER SIDEBAND FILTERS WITH PHASE 180 DEGREE ALIGNMENT

• US 20170338985A1
• Filed: 10/29/2015
• Published: 11/23/2017
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Benjamin P. Wilkerson
• Original Assignee: Benjamin P. Wilkerson
• Inventors: WILKERSON, Benjamin P.
• Granted Patent: US 9,967,120 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 27/233 using non-coherent demodulation
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself
• CPC Class Codes: H04L 27/2334 using filters

Abstract

A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by ¼ of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator.

Claims

1. In the circuit structure of an ultra low power wideband non-coherent BPSK demodulator using first order sideband filters with phase 180 degree alignment, an ultra low power wideband non-coherent binary phase shift keying demodulation circuit comprises:

a sideband separation and lower sideband signal delay unit to output an upper sideband analog signal and a phase delayed analog signal to be delayed with preset phase from a lower sideband analog signal, when a modulation signal in the input of this unit is divided to a lower sideband and an upper sideband by 1^st order filters whose cutoff frequency is same as carrier frequency;

a data demodulation unit to demodulate digital data through a hysteresis circuit that latches an analog pulse signal that is appeared in the phase changing edge of BPSK modulation signal and also is the sum of above delayed lower sideband analog signal and above upper sideband analog signal, because the analog signals are set to phase 180°

; and

a data clock recovery unit to recover data clock using a digitized signal from above delayed lower sideband analog signal and above demodulated digital data signal, also

above sideband separation and lower sideband signal delay unit comprises;

a 1^st order high-pass filter (1^st order HPF) whose cutoff frequency is same as carrier frequency isolates upper sideband from above modulated signal;

a 1^st order low-pass filter (1^st order LPF) whose cutoff frequency is same as carrier frequency isolates lower sideband from above modulated signal; and

a delay circuit to delay with preset phase from a lower sideband analog signal that is the output of above 1^st order LPF,

above data demodulation unit comprises;

an adder to generate an analog pulse signal to appear in the phase changing edge of the modulation signal, and the edge is caused by the sum of analog signals which are above delayed lower sideband analog signal and above upper sideband analog signal because phase difference between above analog signals set to phase 180°

; and

a Schmitt trigger that is a hysteresis circuit to demodulate digital data by latching the analog pulse signal,

above data clock recovery unit comprises;

a comparator to digitize from above delayed lower sideband analog signal; and

an exclusive-NOR gate to compare above delayed lower sideband digital signal with above demodulated digital data signal,

and to be with emphasis in following characteristic;

to demodulate data easily by latching analog pulse signal to include the positive and negative pulses that are generated by adding signals that are above upper sideband analog signal and above delayed lower sideband analog signal that is delayed more ¼

period of carrier frequency by the delay circuit, that'"'"'s why the analog signals are aligned in phase 180°

, through the hysteretic circuit because of above lower sideband analog signal that is separated from above 1^st order LPF is occurred as slow as π

/2 or ¼

period of carrier frequency rather than above upper sideband analog signal that is separated from above 1^st order HPF, and the phase difference of the sideband analog signals whose center is same as carrier frequency is fixed to ¼

period of carrier frequency in range from upper sideband to lower sideband.

2. The ultra low power wideband non-coherent BPSK demodulation circuit of claim 1, wherein above data demodulation unit comprises an adder and a Schmitt trigger that is a hysteresis circuit, and to be with emphasis in the characteristic to demodulate digital data by latching an analog pulse signal that consists of positive and negative pulses which appear in phase changing edge to be based on the difference of analog signals, because of aligning in phase 180°

difference between above delayed lower sideband analog signal and above upper sideband analog signal.

3. The ultra low power wideband non-coherent BPSK demodulation circuit of claim 1, wherein above data clock recovery unit comprises a comparator and an exclusive-NOR gate, and to be with emphasis in the characteristic to recover a data clock through the calculation of above exclusive-NOR gate with above digital data signal and a digital signal to be digitized from above delayed lower sideband analog signal.

4. In the flowchart of an ultra low power wideband non-coherent BPSK demodulation method using first order sideband filters with phase 180 degree alignment, an ultra low power wideband non-coherent binary phase shift keying demodulation method comprises:

a sideband separation and lower sideband signal delay stage to output an upper sideband analog signal and a phase delayed analog signal to be delayed with preset phase from a lower sideband analog signal, when a modulation signal in the input of this stage is divided to a lower sideband and an upper sideband by 1^st order filters whose cutoff frequency is same as carrier frequency;

a data demodulation stage to demodulate digital data through a hysteresis circuit that latches an analog pulse signal that is appeared in the phase changing edge of BPSK modulation signal and also is the sum of above delayed lower sideband analog signal and above upper sideband analog signal, because the signals are set to phase 180°

; and

a data clock recovery stage to recover data clock using a digitized signal from above delayed lower sideband analog signal and above demodulated digital data signal, also

above sideband separation and lower sideband signal delay stage comprises;

a stage to isolate upper sideband from above modulated signal by a 1^st order high-pass filter (1^st order HPF) whose cutoff frequency is same as carrier frequency;

a stage to isolate lower sideband from above modulated signal by 1^st order low-pass filter (1^st order LPF) whose cutoff frequency is same as carrier frequency; and

a delay stage to delay with preset phase from a lower sideband analog signal that is the output of above 1^st order LPF,

above data demodulation stage comprises;

a stage to generate an analog pulse signal to appear in the phase changing edge of the modulation signal by an adder, and the edge is caused by the sum of analog signals which are above delayed lower sideband analog signal and above upper sideband analog signal because phase difference between above analog signals set to phase 180°

; and

a stage to demodulate digital data through latching the analog pulse signal by a Schmitt trigger that is a hysteresis circuit,

above data clock recovery stage comprises;

a stage to convert a digital signal from above delayed lower sideband analog signal by a comparator; and

a stage to recover a data clock for comparing above delayed lower sideband digital signal with above demodulated digital data signal by an exclusive-NOR gate,

and to be with emphasis in following characteristics;

above lower sideband analog signal that is from the output of 1^st order LPF, is occurred as slow as π

/2 or ¼

period of carrier frequency rather than above lower sideband analog signal, and above delayed lower sideband signal is occurred through the delay circuit to delay π

/2 or ¼

period of carrier frequency for finding phase changing edge with aligning phase 180°

difference between the delayed lower sideband signal and the upper sideband signal.