Circuit Board Having an Asymmetric Layer Structure

• US 20170339784A1
• Filed: 12/10/2015
• Published: 11/23/2017
• Est. Priority Date: 12/11/2014
• Status: Active Grant

• Current Assignee: AT&S Austria Technologie & Systemtechnik AG
• Original Assignee: AT&S Austria Technologie & Systemtechnik AG
• Inventors: Zluc, Andreas, Weidinger, Gerald, Schober, Mario, Stahr, Hannes, Schwarz, Timo, Gruber, Benjamin
• Granted Patent: US 9,967,972 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3511 Warping
• CPC Class Codes: H05K 1/0271 : Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 1/0353 : consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
• CPC Class Codes: H05K 1/0366 : reinforced, e.g. by fibres, fabrics H05K1/036 takes precedence
• CPC Class Codes: H05K 1/0373 : containing additives, e.g. fillers H05K1/036 takes precedence
• CPC Class Codes: H05K 1/0393 : Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 1/115 : Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/189 : characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2201/0129 : Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
• CPC Class Codes: H05K 2201/0133 : Elastomeric or compliant polymer elastomeric conductor H05K2201/0314
• CPC Class Codes: H05K 2201/0187 : with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
• CPC Class Codes: H05K 2201/0191 : wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/068 : wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/09136 : Means for correcting warpage
• CPC Class Codes: H05K 3/0017 : Etching of the substrate by chemical or physical means
• CPC Class Codes: H05K 3/0097 : Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards H05K3/0052 takes precedence
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A circuit board is described which includes a layer composite with at least one dielectric layer which includes a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis perpendicular thereto, and which includes a layer thickness along a z-axis which is perpendicular with respect to the x-axis and to the y-axis; and at least one metallic layer which is attached to the dielectric layer in a planar manner. The layer composite along the z-axis is free from a symmetry plane which is oriented in parallel with respect to the xy-plane, and the dielectric layer includes a dielectric material which has an elastic modulus E in a range between 1 and 20 GPa and along the x-axis and along the y-axis a coefficient of thermal expansion in a range between 0 and 17 ppm/K. A method of manufacturing such a circuit board is also described. Further, a method of manufacturing a circuit board structure comprising two asymmetric circuit boards and a method of manufacturing two processed asymmetric circuit boards from a larger circuit board structure is described.

Claims

1. A circuit board, comprising:

a layer composite with

at least one dielectric layer which

comprises a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis which is perpendicular thereto, and

comprises a layer thickness along a z-axis which is perpendicular with respect to the x-axis and to the y-axis; and

at least one metallic layer which is attached to the dielectric layer in a planar manner;

wherein

the layer composite along the z-axis is free from a symmetry plane which is oriented in parallel with respect to the xy-plane, and

the dielectric layer comprises a dielectric material which has

an elastic modulus E in a range between 1 and 20 GPa and

along the x-axis and along the y-axis a coefficient of thermal expansion in a range between 0 and 17 ppm/K.

2. The circuit board of claim 1, wherein

the dielectric material comprises a creeping property which is determined by at least one of the following properties:

(a) a plastic deformability in a range between 0.01% and 10%,

(b) a viscoelastic deformability in a range between 0% and 10%.

3. The circuit claim 1,

wherein the dielectric material is a blend or a copolymer, consisting of at least one first material with a first elastic modulus E and a first coefficient of thermal expansion and a second material with a second elastic modulus E and a second coefficient of thermal expansion, wherein the first elastic modulus is larger than the second elastic modulus and the first coefficient of thermal expansion is smaller than the second coefficient of thermal expansion.

4. The circuit board of claim 3,

wherein the first material comprises a first glass transition temperature and the second material comprises a second glass transition temperature.

5. The circuit board of claim 1, wherein the first material comprises a resin and a hard filler which is located therein.

6. The circuit board of claim 3,

wherein the second material is a thermally curable resin which is connected to a softening substance.

7. The circuit board of claim 1, comprising at least one of the following features:

wherein the value for the elastic modulus E is in a range between 2 and 7 GPa and in particular in a range between 3 and 5 GPa

wherein the coefficient of thermal expansion is in a range between 3 and 10; and

/or

wherein the layer composite comprises an asymmetry with respect to the number of the layers along the z-axis; and

/or

wherein the layer composite comprises an asymmetry with respect to the thicknesses of the single layers along the z-axis; and

/or

wherein the layer composite comprises an asymmetry with respect to the materials of the single layers along the z-axis.

12. The circuit board of claim 1, further comprising:

a component which is embedded in the dielectric and/or in a dielectric core-layer of the circuit board.

13. The circuit board of claim 1, wherein the component is embedded in the dielectric layer.

14. The circuit board of claim, 1, further comprising:

the dielectric core-layer which is attached to the metallic layer and/or to the dielectric layer in a planar manner;

wherein the component is embedded in the dielectric core-layer and the dielectric layer is arranged above or below the dielectric core-layer and the embedded electronic component.

15. The circuit board of claim 14, comprising at least one of the following features:

wherein the component is adhered within the dielectric core-layer; and

/or

wherein the dielectric core-layer comprises a dielectric core material which has a coefficient of thermal expansion from 0 to 11 ppm/k.

17. The circuit board of claim 12, wherein the entire thickness of the layer composite is smaller than approximately 200 μ

m.

18. The circuit board of claim 1, wherein the dielectric layer is a dielectric prepreg-layer and/or the dielectric material is a dielectric prepreg-material.

27. A method of manufacturing two processed circuit boards, the method, comprising:

building up a layer composite comprising

a first circuit board according to claim 1,

a second circuit board according to claim 1, and

a release layer which is arranged between the first circuit board and the second circuit board;

processing the entire layer composite; and

separating the layer composite at the release layer such that a first processed circuit board and a second processed circuit board with respectively one asymmetric layer build-up are generated.

28. The method of claim 27, comprising at least one of the following features:

wherein the built up layer composite comprises a symmetry plane along the z-axis, which is oriented in parallel with respect to the xy-plane, and/or

wherein the release layer comprises a printable adhesion reducing material and wherein the method further comprises

printing the adhesion reducing material on at least a subregion of the first circuit board or on at least a subregion of the second circuit board.

8-11. -11. (canceled)

16. (canceled)

19. A method of manufacturing a circuit board, the method comprising:

building up a superordinated layer composite with

at least one dielectric layer which

comprises a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis which is perpendicular thereto, and

comprises a layer thickness along a z-axis which is perpendicular with respect to the x-axis and to the y-axis; and

at least one metallic layer which is attached to the dielectric layer in a planar manner;

wherein

the layer composite along the z-axis is free from a symmetry plane which is oriented in parallel with respect to the xy-plane, and

the dielectric layer comprises a dielectric material which has

an elastic modulus E in a range between 1 and 20 GPa and

along the x-axis and along the y-axis a coefficient of thermal expansion in a range between 0 and 17 ppm/K.

20. The method of claim 19, further comprising:

forming a recess in the dielectric layer and/or in a dielectric core-layer; and

inserting an electronic component into the recess.

21. The method of claim 20, wherein

the recess is larger than the electronic component, such that after an inserting of the electronic component into the recess, a hollow remains.

22. The method of claim 20, further comprising

if the electronic component is inserted in the dielectric layer,

applying a further dielectric layer on the dielectric layer and the electronic component, wherein

the further dielectric layer has the same properties as the dielectric layer;

and

if the electronic component is embedded in the dielectric core-layer,

applying the dielectric layer on the dielectric core-layer and the electronic component.

23. The method of claim 19, further comprising at least one of the following features:

forming a metallic layer at the dielectric layer, and/or

pressing all layers of the circuit board (200).

24-26. -26. (canceled)

29. (canceled)