STORAGE SYSTEM, METHOD, AND APPARATUS FOR FAST IO ON PCIE DEVICES

• US 20170344510A1
• Filed: 08/04/2016
• Published: 11/30/2017
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Heekwon, KI, Yang Seok
• Granted Patent: US 10,762,030 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/283 Plural cache memories

Abstract

Embodiments of systems and methods for fast input/output (IO) on PCIE devices are described. Such methods include receiving an IO request from a user or application, the IO request comprising instructions for communicating data with a host system, the host system comprising a processing device and a memory device, analyzing information from the IO request in an IO block analyzer to select one of a plurality of communication paths for communicating the data with the host system, defining a routing instruction in a transfer routing information transmitter in response to the selected communication path, communicating the routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of the host system routing the data from the peripheral device to either the processing device or the memory device according to the routing instruction with a data transfer router.

Claims

1. A method for fast input/output (IO) on data handling devices, comprising:

receiving an Input/Output (IO) request from an application, the IO request comprising instructions for communicating data with a host system, the host system comprising a processing device and a memory device;

analyzing information from the IO request in an IO block analyzer to select one of a plurality of communication paths for communicating the data with the host system;

defining a routing instruction in a transfer routing information transmitter in response to the selected communication path;

communicating the routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of the host system; and

routing the data from the peripheral device to either the processing device or the memory device according to the routing instruction with a data transfer router.

2. The method of claim 1, further comprising communicating the data along a first communication path according to a Direct Data IO (DDIO) protocol, wherein the first communication path comprises communicating the data to a Last Level Cache (LLC) associated with the data processing device.

3. The method of claim 1, further comprising communicating the data along a second communication path according to a Direct Memory Access (DMA) protocol, wherein the second communication path comprises communicating the data to the memory device.

4. The method of claim 1, further comprising storing the routing instruction in a routing scratch pad component of a data transfer device coupled to the host system.

5. The method of claim 4, further comprising communicating the routing instruction from the data transfer device to a routing control register of the IIO module.

6. The method of claim 5, wherein communicating the routing instruction comprises setting a routing control bit in the TLP according to the routing instruction stored in the scratch pad.

7. The method of claim 5, further comprising communicating data having a first data characteristic to the data processing device.

8. The method of claim 5, further comprising communicating data having a second data characteristic to the memory device according to the routing instruction stored in the routing control register.

9. A system for fast input/output (IO) on data handling devices, comprising:

a peripheral device comprising an Input/Output (IO) manager to;

receive an Input/Output (IO) request, the IO request comprising instructions for communicating data with a host system, the host system comprising a processing device and a memory device;

analyze information from the IO request to select one of a plurality of communication paths for communicating the data with the host system;

define a routing instruction in response to the selected communication path;

a data transfer device coupled to the peripheral device, and to communicate the routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of the host system.

10. The system of claim 9, wherein the host device is configured to communicate the data along a first communication path according to a Direct Data IO (DDIO) protocol, and wherein the first communication path comprises communicating the data to a Last Level Cache (LLC) associated with the data processing device.

11. The system of claim 10, wherein the host device is configured to communicate the data along a second communication path according to a Direct Memory Access (DMA) protocol, and wherein the second communication path comprises communicating the data to the memory device.

12. The system of claim 9, wherein the data transfer device is configured to store the routing instruction in a routing scratch pad component of a data transfer device coupled to the host system.

13. The system of claim 12, wherein the data transfer device is configured to communicate the routing instruction from the data transfer device to a routing control register of the IIO module.

14. The system of claim 13, wherein the data transfer device is configured to set a routing control bit in the TLP according to the routing instruction stored in the scratch pad.

15. The system of claim 13, further comprising a routing demultiplexer configured to communicate data having a first data characteristic to the data processing device.

16. The system of claim 14 further comprising a routing demultiplexer configured to communicate data having a second data characteristic to the memory device according to the routing instruction stored in the routing control register.

17. An apparatus for fast input/output (IO) on data handling devices, comprising:

a data transfer device coupled to a peripheral device, and configured to communicate a routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of a host system;

wherein the routing instruction comprises a selection of one of a plurality of communication paths for communicating the data with the host system, the selection being determined in response to instructions included in an IO request.

18. The apparatus of claim 17, further comprising a routing scratch pad configured to store the routing instruction.

19. The apparatus of claim 18, further comprising a transfer routing information transmitter configured to insert the routing instruction stored in the routing scratchpad in into a reserved field in the TLP.

20. The apparatus of claim 19, further comprising a DMA engine configured to generate an IO request for communication to the IIO module of the host device, wherein the IIO module is configured to route the IO request according to the routing instruction inserted into the reserved field in the TLP.