HIERARCHICAL LOSSLESS COMPRESSION AND NULL DATA SUPPORT

• US 20170345122A1
• Filed: 05/27/2016
• Published: 11/30/2017
• Est. Priority Date: 05/27/2016
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Seiler, Larry, Surti, Prasoonkumar, Navale, Aditya
• Granted Patent: US 10,282,808 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/302 In image processor or graphics adapter
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management

Abstract

Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.

Claims

1. A graphics processing unit (GPU), the GPU comprising:

one or more graphics cores configured to process computer graphics, the one or more graphics cores being further configured to operate with a memory;

the one or more graphics cores further configured to;

receive an access request to a memory resource that is associated with a metadata stored in the memory, the metadata being configured to encode a null-state indicator value that indicates whether the associated memory resource is null;

read the null-state indicator value of the associated metadata;

determine that the null-state indicator value indicates that the associated memory resource is null;

in response to the null-state determination and the access request being a write operation, ignore the access request.

2. A GPU as recited in claim 1, wherein the one or more graphics cores further configured to:

in response to the null-state determination and the access requesting being a read operation, return a default value instead of reading the memory resource.

3. A GPU as recited in claim 1, wherein the memory resource is a cache and the access-request ignorance includes marking a cacheline of the cache as null.

4. A GPU as recited in claim 1, wherein the memory resource is a cache and the access-request ignorance includes marking a cacheline of the cache as null and the access request is a write request, the one or more graphics cores further configured to:

perform a null-state read on the memory resource that returns an indication that the memory resource contains one or more null addresses;

in response to the read returning the indication that the memory resource contains one or more null addresses, store a default value in a cacheline and set a state in a cache that prevents writes to that cacheline.

5. A GPU as recited in claim 1, wherein the default value is a defined value that is indicative of a null state.

6. A GPU as recited in claim 1, wherein the default value is zero.

7. A GPU as recited in claim 1, wherein:

the metadata being configured to have a size of M bits per compression block and the memory resource is configured to have N bytes per compression block;

the metadata being configured to the encoded value that indicates (2^M−

1) possible different compression states.

8. A GPU as recited in claim 1, wherein the one or more graphics cores further configured to:

in response to the null determination and the access request being a fast clear operation, ignore the access request.

9. A GPU as recited in claim 1, wherein the one or more graphics cores further configured to:

set the null-encoding value of the metadata to indicate that the associated memory resource is in a null state, the setting being in response to an initialization of the memory resources or the memory resource being unmapped from memory.

10. A GPU as recited in claim 1, wherein the one or more graphics cores further configured to:

set the null-encoding value of the metadata to indicate that the associated memory resource is in a non-null state, the setting being in response to the memory resource being mapped to memory.

11. A GPU as recited in claim 1, wherein the memory is part of the GPU.

12. A graphics processing unit (GPU), the GPU comprising:

one or more graphics cores configured to process computer graphics, the one or more graphics cores being further configured to operate with a memory;

the one or more graphics cores further configured to;

receive an access request to a memory resource;

determine that the data of the memory resource is in a null state by accessing an address translation table associated with the memory resource and doing so without a read operation of the memory resource

in response to the null state determination and the access requesting being a read operation, return a default value instead of reading the memory resource.

13. A GPU as recited in claim 12, wherein the memory is part of the GPU.

14. A GPU as recited in claim 12, wherein the memory resource is a cache.

15. A GPU as recited in claim 12, wherein the one or more graphics cores further configured to:

in response to the null determination and the access request being a write operation, ignore the access request.

16. A GPU as recited in claim 12, wherein the default value is a defined value that is indicative of a null state.

17. A GPU as recited in claim 12, wherein the default value is zero.

18. A computer graphics system comprising:

a receiver configured to receive an access request to a memory resource;

a state determiner configured to determine that the data of the memory resource is in a null state by accessing an address translation table associated with the memory resource and doing so without a read operation of the memory resource

a request director configured to, in response to the null state determination and the access requesting being a read operation, return a default value instead of reading the memory resource.

19. A computer graphics system of claim 18, wherein:

the request director configured to, in response to the null determination and the access request being a write operation, directing the system to ignore the access request.

20. A computer graphics system of claim 18, wherein the default value is a defined value that is indicative of a null state.