METHOD OF OPERATING A DISPLAY APPARATUS AND A DISPLAY APPARATUS PERFORMING THE SAME

• US 20170345360A1
• Filed: 04/17/2017
• Published: 11/30/2017
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: LEE, KI-SEOB, YOON, SANGROCK, KIM, DONGIN
• Granted Patent: US 10,217,397 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/08 Arrangements within a display terminal for setting, manually or automatically, display parameters of the display terminal
• CPC Class Codes: G09G 2320/10 Special adaptations of display systems for operation with variable images
• CPC Class Codes: G09G 2320/103 Detection of image changes, e.g. determination of an index representative of the image change
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

In a method of operating a display apparatus, during a first period in which image data is provided to a data driver, a clock embedded data signal having an output differential voltage (“VOD”) set to a first voltage value is applied to the data driver. The VOD of the clock embedded data signal relates to a voltage difference between a high level and a low level of the clock embedded data signal. During a second period in which the image data is not provided to the data driver, the VOD of the clock embedded data signal applied to the data driver is changed to a second voltage value smaller than the first voltage value.

Claims

1. A method of operating a display apparatus, the method comprising:

during a first period in which image data is provided to a data driver, applying a clock embedded data signal having an output differential voltage (“

VOD”

) set to a first voltage value to the data driver, wherein the VOD of the clock embedded data signal relates to a voltage difference between a high level and a low level of the clock embedded data signal; and

during a second period in which the image data is not provided to the data driver, changing the VOD of the clock embedded data signal applied to the data driver to a second voltage value smaller than the first voltage value.

2. The method of claim 1, wherein the second voltage value is equal to or greater than approximately 30% of the first voltage value and is equal to or smaller than approximately 80% of the first voltage value.

3. The method of claim 1, wherein the second period includes:

a first blank period between two consecutive frame periods for displaying two consecutive frame images.

4. The method of claim 3, wherein the second period further includes:

a second blank period between two consecutive line periods for displaying two consecutive line images in one frame image.

5. The method of claim 1, wherein, during the first period, a slew rate of the clock embedded data signal is set to a first time value, wherein the slew rate of the clock embedded data signal relates to a time required to transition from one of the high level and the low level of the clock embedded data signal to the other of the high level and the low level of the clock embedded data signal,

the method further comprising:

during the second period, changing the slew rate of the clock embedded data signal applied to the data driver to a second time value greater than the first time value.

6. The method of claim 5, wherein the second time value is greater than the first time value and is equal to or smaller than approximately three times the first time value.

7. The method of claim 1, wherein the clock embedded data signal applied to the data driver is not toggled during the second period.

8. The method of claim 1, further comprising:

determining whether the image data corresponds to a static image; and

during at least one of the first period and the second period, additionally adjusting the VOD of the clock embedded data signal when the image data corresponds to the static image.

9. The method of claim 8, wherein the first period includes a first frame period for displaying a first frame image, and a second frame period for displaying a second frame image, wherein the first and second frame images are two consecutive frame images,

wherein the second period includes a first blank period between the first frame period and the second frame period, and a second blank period after the second frame period,

wherein the VOD of the clock embedded data signal is set to the first voltage value during the first frame period, and the VOD of the clock embedded data signal is changed from the first voltage value to the second voltage value during the first blank period.

10. The method of claim 9, wherein when the second frame image is substantially the same as the first frame image, the VOD of the clock embedded data signal is changed to a third voltage value during the second frame period,

wherein the third voltage value is smaller than the first voltage value and is greater than the second voltage value.

11. The method of claim 9, wherein when the second frame image is substantially the same as the first frame image, the VOD of the clock embedded data signal is changed to a third voltage value during the second blank period,

wherein the third voltage value is smaller than the second voltage value.

12. The method of claim 1, wherein applying the clock embedded data signal to the data driver during the first period includes:

generating a first high voltage and a first low voltage; and

outputting the clock embedded data signal in response to the first high voltage and the first low voltage,

wherein a difference between the first high voltage and the first low voltage is substantially equal to the first voltage value.

13. The method of claim 12, wherein changing the VOD of the clock embedded data signal during the second period includes:

generating a second high voltage and a second low voltage, wherein the second high voltage has a level lower than that of the first high voltage, and the second low voltage has a level higher than that of the first low voltage; and

outputting the clock embedded data signal in response to the second high voltage and the second low voltage,

wherein a difference between the second high voltage and the second low voltage is substantially equal to the second voltage value.

14. A method of operating a display apparatus, the method comprising:

during a first period in which image data is provided to a data driver, applying a clock signal having an output differential voltage (“

VOD”

) set to a first voltage value to the data driver, wherein the VOD of the clock signal relates to a voltage difference between a high level and a low level of the clock signal; and

during a second period in which the image data is not provided to the data driver, changing the VOD of the clock signal applied to the data driver to a second voltage value smaller than the first voltage value.

15. The method of claim 14, wherein the second voltage value is equal to or greater than approximately 30% of the first voltage value and is equal to or smaller than approximately 80% of the first voltage value.

16. The method of claim 14, wherein, during the first period, a slew rate of the clock signal is set to a first time value, wherein the slew rate of the clock signal relates to a time required to transition from one of the high level and the low level of the clock signal to the other of the high level and the low level of the clock signal,

the method further comprising:

during the second period, changing the slew rate of the clock signal applied to the data driver to a second time value greater than the first time value.

17. The method of claim 16, wherein the second time value is greater than the first time value and is equal to or smaller than approximately three times the first time value.

18. The method of claim 14, wherein applying the clock signal to the data driver during the first period includes:

generating a first high voltage and a first low voltage; and

outputting the clock signal in response to the first high voltage and the first low voltage,

wherein a difference between the first high voltage and the first low voltage is substantially equal to the first voltage value.

19. The method of claim 18, wherein changing the VOD of the clock signal during the second period includes:

generating a second high voltage having a level lower than that of the first high voltage; and

outputting the clock signal in response to the second high voltage and the first low voltage,

wherein a difference between the second high voltage and the first low voltage is substantially equal to the second voltage value.

20. The method of claim 18, wherein changing the VOD of the clock signal during the second period includes:

generating a second high voltage and a second low voltage, wherein the second high voltage has a level lower than that of the first high voltage, and the second low voltage has a level higher than that of the first low voltage; and

outputting the clock signal in response to the second high voltage and the second low voltage,

wherein a difference between the second high voltage and the second low voltage is substantially equal to the second voltage value.

21. A display apparatus, comprising:

a display panel;

a data driver connected to the display panel; and

a timing controller configured to apply a clock embedded data signal to the data driver and configured to set an output differential voltage (“

VOD”

) of the clock embedded data signal, wherein the VOD of the clock signal relates to a voltage difference between a high level and a low level of the clock embedded data signal,

wherein the VOD of the clock embedded data signal is set to a first voltage value during a first period in which image data is provided to the data driver, and the VOD of the clock embedded data signal is changed to a second voltage value smaller than the first voltage value during a second period in which the image data is not provided to the data driver.

22. The display apparatus of claim 21, wherein the second voltage value is equal to or greater than approximately 30% of the first voltage value and is equal to or smaller than approximately 80% of the first voltage value.

23. The display apparatus of claim 21, wherein the second period includes:

a first blank period between two consecutive frame periods for displaying two consecutive frame images on the display panel.

24. The display apparatus of claim 23, wherein the second period further includes:

a second blank period between two consecutive line periods for displaying two consecutive line images in one frame image displayed on the display panel.

25. The display apparatus of claim 21, wherein the timing controller is configured to set a slew rate of the clock embedded data signal to a time required to transition from one of the high level and the low level of the clock embedded data signal to the other of the high level and the low level of the clock embedded data signal,

wherein the slew rate of the clock embedded data signal is set to a first time value during the first period, and the slew rate of the clock embedded data signal is changed to a second time value greater than the first time value during the second period.

26. The display apparatus of claim 25, wherein the second time value is greater than the first time value and is equal to or smaller than approximately three times the first time value.

27. The display apparatus of claim 21, wherein the timing controller is configured to prevent the clock embedded data signal from toggling during the second period.

28. The display apparatus of claim 21, wherein the timing controller is configured to:

determine whether the image data corresponds to a static image, and

during at least one of the first period and the second period, additionally adjust the VOD of the clock embedded data signal when the image data corresponds to the static image.

29. The display apparatus of claim 28, wherein the first period includes a first frame period for displaying a first frame image, and a second frame period for displaying a second frame image, wherein the first and second frame images are two consecutive frame images,

wherein the second period includes a first blank period between the first frame period and the second frame period, and a second blank period after the second frame period,

wherein the VOD of the clock embedded data signal is set to the first voltage value during the first frame period, and the VOD of the clock embedded data signal is changed from the first voltage value to the second voltage value during the first blank period.

30. The display apparatus of claim 29, wherein when the second frame image is substantially the same as the first frame image, the VOD of the clock embedded data signal is changed from the second voltage value to a third voltage value during the second frame period,

wherein the third voltage value is smaller than the first voltage value and is greater than the second voltage value.

31. The display apparatus of claim 29, wherein when the second frame image is substantially the same as the first frame image, the VOD of the clock embedded data signal is changed to a third voltage value during the second blank period,

wherein the third voltage value is smaller than the second voltage value.

32. The display apparatus of claim 21, wherein the timing controller includes:

a voltage generator configured to generate a first high voltage, a first low voltage, a second high voltage and a second low voltage, wherein the second high voltage has a level lower than that of the first high voltage, and the second low voltage has a level higher than that of the first low voltage; and

a clock embedded data signal generator configured to generate the clock embedded data signal in response to the first high voltage, the first low voltage, the second high voltage and the second low voltage.

33. The display apparatus of claim 32, wherein the clock embedded data signal generator is configured to:

during the first period, output the clock embedded data signal having the VOD of the first voltage value in response to the first high voltage and the first low voltage, and

during the second period, output the clock embedded data signal having the VOD of the second voltage value in response to the second high voltage and the second low voltage.

34. A display apparatus, comprising:

a display panel;

a data driver connected to the display panel; and

a timing controller configured to apply image data and a clock signal to the data driver and configured to set an output differential voltage (“

VOD”

) of the clock signal, wherein the VOD of the clock signal relates to a voltage difference between a high level and a low level of the clock signal,

wherein the VOD of the clock signal is set to a first voltage value during a first period in which the image data is provided to the data driver, and the VOD of the clock signal is changed to a second voltage value smaller than the first voltage value during a second period in which the image data is not provided to the data driver.