CIRCUIT WITH COMBINED CELLS AND METHOD FOR MANUFACTURING THE SAME
1 Assignment
0 Petitions
Accused Products
Abstract
In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.
14 Citations
28 Claims
-
1. (canceled)
-
2. (canceled)
-
3. (canceled)
-
4. (canceled)
-
5. (canceled)
-
6. (canceled)
-
7. (canceled)
-
8. (canceled)
-
9. A method, comprising:
-
providing a first cell layout and a second cell layout; the first cell layout comprising; a first higher power line and a first lower power line; a first output pin; at least one first up transistor formed to electrically couple the first output pin to the first higher power line; and at least one first down transistor formed to electrically couple the first output pin to the first lower power line; the second cell layout comprising; a second higher power line and a second lower power line; a second output pin; at least one second up transistor formed to electrically couple the second output pin to the second higher power line; at least one second down transistor formed to electrically couple the second output pin to the second lower power line; the at least one second up transistor and the at least one second down transistor comprising a first gate line; combining the first cell layout and the second cell layout into a third cell layout comprising; non-selectively electrically coupling the first gate line to the first output pin to form a first node; and generating, by at least one processor, a design layout in which the third cell layout is used at different locations. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. A method, comprising:
-
providing a first cell layout and a second cell layout; the first cell layout comprising; a first higher power line and a first lower power line; a first output pin; at least one first up transistor formed to electrically couple the first output pin to the first higher power line; and at least one first down transistor formed to electrically couple the first output pin to the first lower power line; the second cell layout comprising; a second higher power line and a second lower power line; a second output pin; at least one second up transistor formed to electrically couple the second output pin to the second higher power line; at least one second down transistor formed to electrically couple the second output pin to the second lower power line; and the at least one second up transistor and the at least one second down transistor comprising a first gate line; combining the first cell layout and the second cell layout into a third cell layout comprising; non-selectively electrically coupling the first gate line to the first output pin to form a first node; and generating, by at least one processor, a design layout in which the third cell layout is used; and manufacturing an integrated circuit chip based on the design layout. - View Dependent Claims (21, 22, 23)
-
-
24. A method, comprising:
providing a first cell layout and a second cell layout; the first cell layout comprising; a first output pin; the second cell layout comprising; a higher power line and a lower power line; a second output pin; at least one up transistor formed to electrically couple the second output pin to the higher power line; at least one down transistor formed to electrically couple the second output pin to the lower power line; and the at least one up transistor and the at least one down transistor comprising a first gate line; non-selectively electrically coupling the first gate line to the first output pin to form a third cell; and generating, by at least one processor, a design layout according to the third cell layout. - View Dependent Claims (25, 26, 27, 28)
Specification