SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20170345945A1
• Filed: 12/08/2016
• Published: 11/30/2017
• Est. Priority Date: 05/30/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Seung Hun, KIM, Dong Woo, SUH, Dong Chan, KIM, Sun Jung
• Granted Patent: US 10,319,863 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/765 with specified cross-sectional profile, e.g. belt-shaped
• CPC Class Codes: Y10S 977/938 : Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

Claims

1. A transistor, comprising:

a drain;

a source;

a gate electrode; and

a first nanowire between the source and drain,

wherein the first nanowire has a first section with a first thickness and a second section with a second thickness different from the first thickness, and wherein the second section is between the first section and at least one of the source or drain, the first nanowire to include a channel when a voltage is applied to the gate electrode.

2. The transistor as claimed in claim 1, wherein:

the first section overlaps the gate electrode, and

the second section does not overlap the gate electrode.

3. The transistor as claimed in claim 1, further comprising:

at least one gate spacer,

wherein the second section overlaps the at least one gate spacer.

4. The transistor as claimed in claim 3, wherein the second section is in a hole of the at least one spacer.

5. The transistor as claimed in claim 1, wherein:

the first section has a first surface,

the second section has a second surface, and

the first and second surfaces are in different planes.

6. The transistor as claimed in claim 1, wherein the first and second sections of the first nanowire are arranged to have substantially a barbell shape.

7. The transistor as claimed in claim 1, wherein the first nanowire has a third section between the first and second sections, and wherein the third section is inclined relative to the first and second sections.

8. The transistor as claimed in claim 1, wherein:

the first nanowire includes at least one dimple, and

the at least one dimple is between a surface of the first section and a surface of the second section.

9. The transistor as claimed in claim 1, wherein the second section has rounded surfaces.

10. The transistor as claimed in claim 1, further comprising a fin-shaped pattern overlapping at least one of the source, the drain, or the first nanowire.

11. The transistor as claimed in claim 1, further comprising:

a second nanowire between the source and drain and overlapping the first nanowire.

12. The transistor as claimed in claim 11, wherein the second nanowire has a different shape from the first nanowire.

13. The transistor as claimed in claim 11, wherein the first and second nanowires have different cross-sectional areas.

14. The transistor as claimed in claim 1, wherein the second thickness is greater than the first thickness.

15-25. -25. (canceled)

26. A semiconductor device, comprising:

a first region including a first transistor, the first transistor including a first gate electrode, a first source, a first drain, and a first nanowire between the first source and the first drain, the first nanowire having a first shape; and

a second region including a second transistor, the second transistor including a second gate electrode, a second source, a second drain, and a second nanowire between the second source and the second drain, the second nanowire having a second shape different from the first shape.

27. The semiconductor device as claimed in claim 26, wherein the first and second nanowires include different materials.

28. The semiconductor device as claimed in claim 26, wherein:

the first transistor is an NMOS transistor, and

the second transistor is a PMOS transistor.

29. The semiconductor device as claimed in claim 26, wherein:

the first transistor includes a silicon (Si) channel region, and

the second transistor includes an silicon germanium (SiGe) channel region.

30-36. -36. (canceled)