Independent Control of Branch FETs for RF Performance Improvement

• US 20170346486A1
• Filed: 06/09/2017
• Published: 11/30/2017
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Conry, Michael, Roberts, Kevin, Comfoltey, Edward Nicholas
• Granted Patent: US 10,171,076 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/44 Transmit/receive switching
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04B 2001/485 inhibiting unwanted transmission

Abstract

A FET-based RF switch architecture and method that provides for independent control of FETs within component branches of a switching circuit. With independent control of branch FETs, every RF FET in an inactive branch that is in an “open” (capacitive) state can be shunted to RF ground and thus mitigate impedance mismatch effects. Providing a sufficiently low impedance to RF ground diminishes such negative effects and reduces the sensitivity of the switch circuit to non-matched impedances.

Claims

1. A switch circuit including:

(a) at least two switching branches, each switching branch including;

(1) at least two gateway switches configured to be connected to respective external circuit elements;

(2) a common node coupled to the at least two gateway switches; and

(3) a shunt circuit connected to the common node and programmatically settable to selectively isolate such switching branch independently of any other switching branch.

2. The invention of claim 1, wherein the shunt circuit of at least one switching branch is selectively configured to not isolate such switching branch when such switching branch is inactive.

3. The invention of claim 1, wherein the shunt circuit of a first switching branch includes a corresponding first signal port, and the shunt circuit of a second switching branch includes a corresponding second signal port, and wherein in at least one mode of operation, the shunt circuit of the first switching branch is programmatically set to couple the first signal port to a first external circuit element through one of the at least two gateway switches of the first switching branch, while the shunt circuit of the second switching branch is programmatically set to concurrently couple the second signal port to a second external circuit element through one of the at least two gateway switches of the second switching branch.

6. The invention of claim 1, 4, or 5, wherein at least one switch includes a stack of series connected FETs.

7. The invention of claim 1, 4, or 5, wherein the circuit is fabricated as an integrated circuit using a silicon-on-insulator fabrication process.

8. The invention of claim 1, 4, or 5, wherein at least one switch includes a variable impedance FET programmatically settable to an impedance between the impedance presented by the FET when in a fully open state or when in a fully closed state.

9. The invention of claim 1, 4, or 5, wherein at least one external circuit element includes an antenna.

11. The method of claim 1, further including, in a second mode of operation, selectively configuring the shunt circuit of at least one switching branch to not isolate such switching branch when such switching branch is inactive.

12. The method of claim 1, wherein the shunt circuit of a first switching branch includes a corresponding first signal port, and the shunt circuit of a second switching branch includes a corresponding second signal port, and further including, in at least one mode of operation, programmatically setting the shunt circuit of the first switching branch to couple the first signal port to a first external circuit element through one of the at least two gateway switches of the first switching branch, while programmatically setting the shunt circuit of the second switching branch to concurrently couple the second signal port to a second external circuit element through one of the at least two gateway switches of the second switching branch.

4. A switching circuit including:

(a) a plurality of gateway switches each configured to be connected to respective external circuit elements;

(b) at least one common node, each coupled to at least some of the plurality of gateway switches;

(c) a plurality of signal ports; and

(d) a plurality of shunt circuits, each connected between at least one common node and a corresponding one of the plurality of signal ports, and each programmatically settable to selectively isolate such corresponding signal port independently of any other signal port.

5. A switchable branch circuit including:

(a) at least two gateway switches configured to be connected to respective external circuit elements;

(b) a common port node connected to the at least two gateway switches; and

(c) a shunt circuit connected to the common port node;

wherein, within the switchable branch circuit;

(1) in an inactive mode, the shunt circuit is programmatically set to a closed state and the at least two gateway switches are programmatically set to an open state so as to isolate the common port node from the external circuit elements and to shunt the common port node to circuit ground in order to isolate the common port node with respect to any external circuit elements connected to the gateway switches, and

(2) in an active mode, the shunt circuit is programmatically set to an open state and at least one gateway switch is programmatically set to a closed state so as to enable coupling of the common port node through such at least one closed state gateway switch to the respective external circuit elements connected to such at least one closed state gateway switch.

10. A method for operating a switch circuit including at least two switching branches, including:

(a) configuring each switching branch with at least two gateway switches to be connected to respective external circuit elements;

(b) configuring each switching branch with a common node coupled to the at least two gateway switches of such switching branch; and

(c) in a first mode of operation, programmatically selectively isolating at least one switching branch independently of any other switching branch through a programmable shunt circuit connected to the common node of the at least one isolated switching branch.

15. The method of claim 10, 13, or 14, wherein at least one switch includes a stack of series connected FETs.

16. The method of claim 10, 13, or 14, further including fabricating the circuit as an integrated circuit using a silicon-on-insulator fabrication process.

17. The method of claim 10, 13, or 145, wherein at least one switch includes a variable impedance FET programmatically settable to an impedance between the impedance presented by the FET when in a fully open state or when in a fully closed state.

18. The method of claim 10, 13, or 14, wherein at least one external circuit element includes an antenna.

13. A method for operating a switch circuit, including:

(a) providing a plurality of gateway switches each configured to be connected to respective external circuit elements;

(b) providing at least one common node, each coupled to at least some of the plurality of gateway switches;

(c) providing a plurality of signal ports; and

(d) providing a plurality of shunt circuits, each connected between at least one common node and a corresponding one of the plurality of signal ports, and each programmatically settable to selectively isolate such corresponding signal port independently of any other signal port.

14. A method for operating a switchable branch circuit including:

(a) providing at least two gateway switches configured to be connected to respective external circuit elements;

(b) providing a common port node connected to the at least two gateway switches; and

(c) providing a shunt circuit connected to the common port node;

wherein, within the switchable branch circuit;

(1) in an inactive mode, programmatically setting the shunt circuit to a closed state and programmatically setting the at least two gateway switches to an open state so as to isolate the common port node from the external circuit elements and to shunt the common port node to circuit ground in order to isolate the common port node with respect to any external circuit elements connected to the gateway switches, and

(2) in an active mode, programmatically setting the shunt circuit to an open state and programmatically setting at least one gateway switch to a closed state so as to enable coupling of the common port node through such at least one closed state gateway switch to the respective external circuit elements connected to such at least one closed state gateway switch.