MEMORY CONTROLLER, AND MEMORY MODULE AND PROCESSOR INCLUDING THE SAME

• US 20170352403A1
• Filed: 07/20/2016
• Published: 12/07/2017
• Est. Priority Date: 06/01/2016
• Status: Abandoned Application

• Current Assignee: Memray Corporation, University-Industry Foundation Yonsei University
• Original Assignee: Industry-Academic Cooperation Foundation Yonsei University, Memray Corporation
• Inventors: LEE, Jaesoo, JUNG, Myoungsoo, PARK, Gyuyoung
• Application Number:
  US15/214,580
• Publication Number:
  US 20170352403A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/40607 Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

A memory controller of a memory device that uses a phase change memory and includes a memory cell array partitioned into a plurality of partitions is provided. A write request that request a data write to the memory device and a read request which request a data read from the memory device are inserted to a request queue. A scheduler, in a case that a conflict check condition including a first condition that a write operation is being performed in a first partition among the plurality of partitions is satisfied, creates a read command for a second partition based on a read request for the second partition when the request queue includes the read request for the second partition. The second partition is a partition, in which a read operation does not conflict with the write operation in the first partition, among the plurality of partitions.

Claims

1. A memory controller of a memory device that uses a phase change memory and includes a memory cell array partitioned into a plurality of partitions, the memory controller comprising:

a request queue to which a write request that requests a data write to the memory device and a read request that requests a data read from the memory device are inserted; and

a scheduler that, in a case that a conflict check condition including a first condition that a write operation is being performed in a first partition among the plurality of partitions is satisfied, creates a read command for a second partition based on a read request for the second partition when the request queue includes the read request for the second partition, the second partition being a partition, in which a read operation does not conflict with the write operation in the first partition, among the plurality of partitions.

2. The memory controller of claim 1, wherein the read request used for creating the read command includes a read request that is selected according to a predetermined policy from among read requests for the second partition.

3. The memory controller of claim 1, wherein the memory device further includes a plurality of row data buffers that store data read from the memory cell array, and

wherein the scheduler, when there is a row data buffer which data corresponding to the read request for the second partition hit among the plurality of row data buffers, selects the row data buffer.

4. The memory controller of claim 1, wherein the memory device further includes a plurality of row data buffers that store data read from the memory cell array, and

wherein the scheduler, when data corresponding to the read request for the second partition do not hit the plurality of row data buffers, stores the data corresponding to the read request for the second partition in a row data buffer that stores oldest data among the plurality of row data buffers.

5. The memory controller of claim 1, wherein the conflict check condition further includes a second condition that the request queue does not include a read request for a word line that is open for a read operation while the write operation is being performed in the first partition.

6. The memory controller of claim 5, wherein the scheduler creates a read command based on the read request for the open word line when the first condition is satisfied and the second condition is not satisfied.

7. The memory controller of claim 1, wherein in a case that the write operation is not being performed in the memory device, the scheduler, when an oldest request in the request queue is a write request, creates a write command based on the oldest write request.

8. The memory controller of claim 7, wherein the scheduler creates the write command based on the oldest write request and write requests for memory cells that can be written at the same time with the oldest write request.

9. The memory controller of claim 1, wherein in a case that the write operation is not being performed in the memory device, the scheduler, when an oldest request in the request queue is a read request, creates a read command.

10. The memory controller of claim 9, wherein the scheduler, when the request queue includes a read request for a word line that is open for a read operation, creates the read command based on the read request for the open word line.

17. A memory module comprising:

the memory controller according to claim 1; and

the memory device.

18. A processor comprising a memory controller according to claim 1, wherein the processor is connected to the memory device through a system bus.

11. A memory controller of a memory device that uses a phase change memory and includes a memory cell array partitioned into a plurality of partitions, the memory controller comprising:

a request queue to which a write request that requests a data write to the memory device and a read request that requests a data read from the memory device are inserted; and

a scheduler that creates a read command based on a predetermined read request when a write operation is being performed in a first partition among the plurality of partitions.

12. The memory controller of claim 11, wherein the predetermined read request includes a read request for a second partition, in which a read operation does not conflict with the write operation in the first partition, among the plurality of partitions.

13. The memory controller of claim 12, wherein the read request used for creating the read command includes a read request that is selected according to a predetermined policy from among read requests for the second partition.

14. The memory controller of claim 11, wherein the predetermined read request includes a read request for a word line that is open for a read operation.

15. The memory controller of claim 11, wherein in a case that the write operation is not being performed in the memory device, the scheduler, when an oldest request in the request queue is a write request, creates a write command based on the oldest write request.

16. The memory controller of claim 15, wherein the scheduler creates the write command based on the oldest write request and write requests for memory cells that can be written at the same time with the oldest write request.