NON-VOLATILE MEMORY WITH CUSTOMIZED CONTROL OF INJECTION TYPE OF DISTURB DURING PROGRAM VERIFY FOR IMPROVED PROGRAM PERFORMANCE

• US 20170352430A1
• Filed: 06/03/2016
• Published: 12/07/2017
• Est. Priority Date: 06/03/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Chen, Hong-Yan, Dong, Yingda
• Granted Patent: US 10,026,487 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Abstract

A non-volatile memory system includes one or more control circuits configured to program memory cells and verify the programming. The verifying of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for verification, and performing a sensing operation for the memory cell selected for verification in response to the compare signal.

Claims

1. A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells; and

one or more control circuits in communication with the memory cells, the one or more control circuits configured to program the memory cells and verify the programming;

to verify the programming the one or more control circuits are configured to apply one or more voltages to perform boosting of a channel region associated with an unselected memory cell, allow the boosting of the channel region for a portion of time while applying the one or more voltages, temporarily prevent an increase in the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, apply a compare signal to the memory cell selected for verification and the unselected memory cell, and perform a sensing operation for the memory cell selected for verification in response to the compare signal.

2. The non-volatile storage apparatus of claim 1, wherein:

the non-volatile memory cells are arranged in groups of connected non-volatile memory cells;

the memory cell selected for verification is in a selected group of connected non-volatile memory cells;

the selected group of connected non-volatile memory cells has a first end and a second end;

the one or more control circuits are configured to program memory cells in the selected group in an order from the first end to the second end; and

the one or more control circuits are configured to temporarily prevent the increase in the boosting of the channel region while applying the one or more voltages for a duration of time based on position of the memory cell selected for verification with respect to the first end of the selected group.

3. The non-volatile storage apparatus of claim 1, further comprising:

word lines, the non-volatile memory cells are arranged in groups of connected non-volatile memory cells, the word lines are connected to the groups of connected non-volatile memory cells,

the one or more control circuits are configured to temporarily prevent the increase in the boosting of the channel region while applying the one or more voltages for a duration of time based on word line position of the memory cell selected for verification.

4. The non-volatile storage apparatus of claim 1, wherein:

the non-volatile memory cells are arranged in NAND strings; and

the one or more control circuits are configured to temporarily prevent the increase in the boosting of the channel region while applying the one or more voltages to perform boosting for a duration of time based on position in a NAND string of the memory cell selected for verification.

5. The non-volatile storage apparatus of claim 1, further comprising:

word lines, the non-volatile memory cells are arranged in groups of connected non-volatile memory cells, the groups include a first side and a second side, the one or more control circuits are configured to operate the word lines as at least two sets of word lines comprising a first set of word lines connected to the first side of the groups of connected non-volatile memory cells and a second set of word lines connected to the second side of the groups of connected non-volatile memory cells, the one or more control circuits are configured to temporarily prevent the increase in the boosting of the channel region for a first duration of time if the memory cell selected for verification is connected to the first set and for a second duration of time if the memory cell selected for verification is connected to the second set.

6. The non-volatile storage apparatus of claim 5, wherein:

the word lines include a third set of word lines, the one or more control circuits are configured to temporarily prevent the increase in the boosting of the channel region for a third duration of time if the memory cell selected for verification is connected to the third set of word lines.

7. The non-volatile storage apparatus of claim 1, further comprising:

word lines, the non-volatile memory cells are arranged in groups of connected non-volatile memory cells, the groups include a first side and a second side, the one or more control circuits are configured to operate the word lines as three sets of word lines comprising a first set of word lines connected to the first side of the groups of connected non-volatile memory cells and a second set of word lines connected to the second side of the groups of connected non-volatile memory cells as well as a third set of word lines between the first set and the second set, the one or more control circuits are configured to temporarily prevent the increase in the boosting of the channel region for a first duration of time if the memory cell selected for verification is connected to the first set and for a second duration of time if the memory cell selected for verification is connected to the second set, if the memory cell selected for verification is connected to the third set then the one or more control circuits are configured to temporarily prevent the increase in the boosting of the channel region for the first duration during some iterations of a programming process and for the second duration during other iterations of the programming process.

8. The non-volatile storage apparatus of claim 7, wherein:

the groups of connected non-volatile memory cells are vertical NAND strings;

the one or more control circuits are configured to program memory cells in the selected group in an order from the first side to the second side; and

the first duration is longer than the second duration.

10. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits are configured to temporarily prevent the increase in the boosting of the channel region by interrupting the boosting after it has started and subsequently allowing the boosting to continue.

11. The non-volatile storage apparatus of claim 1, wherein:

the unselected memory cell is part of a NAND string; and

the channel region associated with the unselected memory cell is a channel region for the NAND string.

12. The non-volatile storage apparatus of claim 1, wherein:

the plurality of non-volatile memory cells are arranged in a monolithic three dimensional memory structure.

13. The non-volatile storage apparatus of claim 1, wherein:

the plurality of non-volatile memory cells are arranged in vertical NAND strings of a monolithic three dimensional memory structure.

9. A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells;

select gates;

word lines, the non-volatile memory cells are arranged in NAND strings that include one or more select gates, the word lines are connected to the non-volatile memory cells of the NAND strings;

select lines connected to the select gates;

one or more control circuits in communication with the memory cells, select gates, word lines and select lines;

the one or more control circuits are configured to program the memory cells and verify the programming;

wherein the one or more control circuits are configured to verify the programming by applying a voltage to one or more select lines for selected NAND strings to turn on one or more select gates for selected NAND strings, applying a voltage to one or more select lines for unselected NAND strings to turn off one or more select gates for unselected NAND strings, applying and increasing a boosting voltage to unselected word lines to boost channels of unselected NAND strings such that the unselected word lines are connected to the selected NAND strings and the unselected NAND strings, applying a compare voltage to a selected word line connected to the selected NAND strings and the unselected NAND strings, sensing a threshold voltage of selected memory cells in the selected NAND strings in response to the compare voltage, and while increasing the boosting voltage, temporarily changing the voltage applied to the select lines for unselected NAND strings to temporarily turn on the select gates for unselected NAND strings in order to interrupt boosting of the channels of the unselected NAND strings for a duration of time based on position of the selected word line.

14. A method of operating non-volatile storage, comprising:

programming non-volatile memory cells; and

verifying the programming, the verifying the programming comprises;

applying a voltage to one or more select gates for selected groups of memory cells to turn on the one or more select gates for selected groups of memory cells,

applying a voltage to one or more select gates for unselected groups of memory cells to turn off the one or more select gates for the unselected groups of memory cells,

applying and increasing a boosting voltage to unselected control lines to boost channels of unselected groups of memory cells, the unselected control lines are connected to the selected groups of memory cells and the unselected groups of memory cells,

applying a compare voltage to a selected control line connected to the selected groups of memory cells and the unselected groups of memory cells,

sensing a threshold voltage of selected memory cells in the selected groups of memory cells in response to the compare voltage, and

while increasing the boosting voltage, temporarily changing the voltage applied to the select gates for unselected groups of memory cells to temporarily turn on the select gates for unselected groups of memory cells in order to prevent boosting of the channels of the unselected groups of memory cells for a duration of time based on position of the selected control line.

15. The method of claim 14, wherein:

the temporarily changing the voltage applied to the select gates for unselected groups of memory cells includes applying a voltage spike to the select gates for unselected groups of memory cells.

16. The method of claim 14, wherein:

the temporarily changing the voltage applied to the select gates for unselected groups of memory cells temporarily interrupts boosting that has already started.

17. The method of claim 14, wherein:

the unselected control lines and the selected control line are arranged as a group of control lines having a first edge and a second edge memory cells connected to the unselected control lines and the selected control line are programmed from the first edge to the second edge, the group of control lines are divided into a first zone and a second zone, the first zone is closer to the first edge than the second zone; and

the duration of time is a first duration if the selected control line is in the first zone and a second duration if the selected control line is in the second zone, the first duration is longer than the second duration.

18. The method of claim 14, wherein:

the unselected control lines and the selected control line are arranged as a group of control lines having a first edge and a second edge, the group of control lines are divided into a first zone, a second zone and a third zone, the first zone is closer to the first edge than the second zone, the second zone is closer to the second edge than the first zone, the third zone is between the first zone and the second zone; and

the duration of time is a first duration if the selected control line is in the first zone and a second duration if the selected control line is in the second zone, the first duration is longer than the second duration, the duration of time is the first duration for some iterations of a programming process and the second duration for other iterations of the programming process if the selected word line is in the third zone.

19. The method of claim 14, wherein:

the control lines are word lines; and

the non-volatile memory cells are arranged in vertical NAND strings of a monolithic three dimensional memory structure.

20. (canceled)

21. A non-volatile storage apparatus, comprising:

a plurality of word lines;

a plurality of groups of connected non-volatile memory cells connected to the word lines; and

one or more control circuits in communication with the groups of connected memory cells and the word lines, the one or more control circuits configured to program the memory cells and verify the programming;

to verify the programming the one or more control circuits are configured to apply one or more voltages that increase over time to the word lines in order to perform boosting of a channel region associated with an unselected groups of connected memory cells and initially allow the boosting of channel regions of unselected groups of connected memory cells for a portion of time while applying the one or more voltages that increase in time, the one or more control circuits are configured to apply a compare signal to a memory cell selected for verification and unselected memory cells connected to a selected word line and perform a sensing operation for the memory cell selected for verification in response to the compare signal, the one or more control circuits are configured to temporarily interrupt the boosting for a period of time based on word line position of the selected word line.