SEMICONDUCTOR DEVICE USING A PARALLEL BIT OPERATION AND METHOD OF OPERATING THE SAME
First Claim
Patent Images
1. A memory device comprising:
- a memory cell array comprising a plurality of memory cells; and
an internal operation circuit configured to perform both a test operation and an internal operation using a parallel bit operation of simultaneously comparing a plurality of bits,wherein the internal operation circuit is configured to perform the test operation in a test mode of the memory device and the internal operation in an internal operation mode other than the test mode of the memory device based on a command signal received from an outside of the memory device.
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Abstract
A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.
11 Citations
20 Claims
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1. A memory device comprising:
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a memory cell array comprising a plurality of memory cells; and an internal operation circuit configured to perform both a test operation and an internal operation using a parallel bit operation of simultaneously comparing a plurality of bits, wherein the internal operation circuit is configured to perform the test operation in a test mode of the memory device and the internal operation in an internal operation mode other than the test mode of the memory device based on a command signal received from an outside of the memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor device comprising:
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an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits, and to perform an internal operation comprising a comparison operation with respect to external data in a normal mode other than the test mode by using the parallel bit operation, wherein the internal operation circuit comprises; a mode selector configured to set a mode of the internal operation circuit as the test mode or an internal operation mode of the normal mode; a parallel bit comparator configured to perform a parallel bit comparison (PBC) between data read out from a memory cell array and the external data received from an outside of the semiconductor device by using the parallel bit operation; and a result generator configured to output a comparison result obtained by the parallel bit comparator. - View Dependent Claims (15)
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16. A memory device comprising:
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a memory cell array comprising a plurality of memory cells; and an internal operation circuit including a parallel bit comparator configured to simultaneously compare first data from a first set of memory cells of the memory cell array with second data received from outside the memory device in an internal operation mode of the memory device, wherein the parallel bit comparator is configured to operate in a test mode of the memory device for a parallel bit test operation. - View Dependent Claims (17, 18, 19, 20)
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Specification