METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC SEMICONDUCTOR CHIP

• US 20170352535A1
• Filed: 11/11/2015
• Published: 12/07/2017
• Est. Priority Date: 11/20/2014
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Hertkorn, Joachim
• Granted Patent: US 10,535,515 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

A method of producing an optoelectronic semiconductor chip includes in order: A) creating a nucleation layer on a growth substrate, B) applying a mask layer on to the nucleation layer, C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer, E) growing a multiple quantum well structure on the coalescence layer, F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and G) detaching the growth substrate and creating a roughening by etching.

Claims

1-15. -15. (canceled)

16. A method of producing an optoelectronic semiconductor chip comprising in order:

A) creating a nucleation layer on a growth substrate,

B) applying a mask layer on to the nucleation layer, wherein the mask layer is formed by a plurality of mask islands,

C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by the mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, which when seen in a top view form a lattice and have trapezoidal cross-sectional surfaces,

D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer,

E) growing a multiple quantum well structure on the coalescence layer,

F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and

G) detaching the growth substrate and creating a roughening by etching, wherein the mask layer serves as an etching mask,

wherein the mirror islands comprises a transparent, dielectric material and are electrically insulating in a direction perpendicular to the multiple quantum well structure when the semiconductor chip is used for its intended purpose.

17. The method according to claim 16,

wherein the lattice formed by the ribs lies above the contact regions in registry therewith, seen in a top view, and

the mirror islands are formed on a side composed of a dielectric material facing towards the multiple quantum well structure.

18. The method according to claim 16, wherein

the nucleation layer comprises or consists of one or more partial layers of aluminum nitride, aluminum oxynitride and/or AlGaN,

the mask layer is made of a silicon oxide and/or a silicon nitride,

the coalescence layer is made of GaN or of GaN and AlGaN,

the multiple quantum well structure is based on the material system AlInGaN and generates blue light, and

between the mirror and the multiple quantum well structure a top layer is located, which is made of p-doped GaN and, in some areas, extends into the multiple quantum well structure.

19. The method according to claim 18, wherein

the contact regions comprise or consist of Ag, Al and/or ZnO and are in direct contact with the top layer,

the top layer is applied directly on to the multiple quantum well structure,

the mirror islands are in direct contact with the top layer and, in a direction perpendicular to the multiple quantum well structure, are electrically insulating, and

the mirror islands are covered on a side facing away from the multiple quantum well structure by a closing mirror layer composed of a material of the contact regions.

20. The method according to claim 18, wherein, in the region of the mirror islands, in a direction away from the top layer, the mirror consists of partial layers in the specified order:

100 nm to 500 nm SiO₂,

1 nm to 20 nm ZnO,

50 nm to 300 nm Ag, and

2 nm to 150 nm ZnO.

21. The method according to claim 16, wherein the lattice composed of upper sides of the ribs facing away from the growth substrate and the contact regions have a regular hexagonal structure, seen in a top view.

22. The method according to claim 16, wherein the mask islands seen in a top view are circular and arranged in a regular hexagonal lattice, an average diameter of the mask islands is 0.5 μ

m to 3 μ

m, and an average distance between adjacent mask islands is 0.5 μ

m to 3 μ

m.

23. The method according to claim 22,

wherein, after step C) and before step D), a width of the upper sides of the ribs is smaller than the average distance between adjacent mask islands of the mask layer, and

seen in top view, a surface proportion of the upper sides of the ribs is no more than 10%, based on the total surface area of the nucleation layer.

24. The method according to claim 16,

wherein, after step C) and before step D), the ribs are formed in free spaces between the upper sides in the form of truncated pyramids, and

step C) is carried out at a lower growth temperature than step D).

25. The method according to claim 16,

wherein, before step G), a carrier is applied on the mirror,

current is applied to the multiple quantum well structure exclusively via the carrier, and

electrical connections that apply current to a side of the multiple quantum well structure facing away from the carrier are fed through the mirror and the multiple quantum well structure.

26. The method according to claim 16,

wherein, on a side of the coalescence layer facing away from the growth substrate, a higher dislocation density is present in regions over the ribs than in regions between the ribs, and

the multiple quantum well structure has a higher density of V-defects in the regions over the ribs than in the regions between the ribs.

27. The method according to claim 26, wherein the regions with the higher density of V-defects, starting from the contact regions, conduct current into the multiple quantum well structure in a direction perpendicular to the mirror.

28. The method according to claim 26,

wherein the mask layer is partially present in the finished semiconductor chip,

at least 90% of the nucleation layer is removed and the roughening does not extend into the multiple quantum well structure, and

the V-defects extend from the mirror through the multiple quantum well structure to the coalescence layer.

29. The method according to claim 16,

wherein the mask islands of the mask layer or a partial layer of the mask islands have/has an absorptance of at least 60% for at least a partial region of the spectrum between 240 nm and 480 nm seen in transmission, and

the nucleation layer and the growth substrate have an absorptance of no more than 5% in this partial region of the spectrum, seen in transmission.

30. An optoelectronic semiconductor chip produced by the method according to claim 29.

31. A method of producing an optoelectronic semiconductor chip comprising in order:

A) creating a nucleation layer on a growth substrate,

B) applying a mask layer on to the nucleation layer, wherein the mask layer is formed by a plurality of mask islands,

C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by the mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, which when seen in a top view form a lattice and which have trapezoidal cross-sectional surfaces,

D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer,

E) growing a multiple quantum well structure on the coalescence layer,

F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and

G) detaching the growth substrate and creating a roughening by etching, wherein the mask layer serves as an etching mask.