FinFETs with Strained Well Regions

• US 20170352596A1
• Filed: 08/28/2017
• Published: 12/07/2017
• Est. Priority Date: 02/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Yi-Jing, Wu, Cheng-Hsien, Ko, Chih-Hsin, Wann, Clement Hsingjen
• Granted Patent: US 10,158,015 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/432 Heterojunction gate for field effect devices
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/7789 : the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
• CPC Class Codes: H01L 29/7842 : means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Claims

1. A device comprising:

a substrate;

insulation regions over a portion of the substrate;

a first semiconductor region between the insulation regions;

a second semiconductor region over and adjoining the first semiconductor region, wherein the second semiconductor region comprises an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin;

a third semiconductor region over the semiconductor fin, wherein the third semiconductor region comprises at least a first sub layer doped with an n-type impurity, wherein the first, the second and the third semiconductor regions are formed of different materials;

a silicon cap over the third semiconductor region, wherein the silicon cap is free from n-type and p-type impurities; and

a source region and a drain region on opposite sides of the semiconductor fin.

2. The device of claim 1, wherein the second semiconductor region is intrinsic.

3. The device of claim 1, wherein the third semiconductor region extends from the source region to the drain region.

4. The device of claim 1, wherein the first semiconductor region and the third semiconductor region comprise silicon germanium, and have germanium atomic percentages higher than an atomic percentage of the second semiconductor region.

5. The device of claim 1, wherein the third semiconductor region comprises:

a second sub layer on sidewalls and a top surface of the semiconductor fin, wherein the first sub layer is over the second sub layer, and the second sub layer is an un-doped layer substantially free from n-type impurities.

6. The device of claim 5, wherein the third semiconductor region further comprises a third sub layer overlying the first sub layer, and the third sub layer is substantially free from n-type impurities.

7. The device of claim 6, wherein each of the first sub layer, the second sub layer, and the third sub layer comprises silicon germanium, and atomic percentages of silicon in the first sub layer, the second sub layer, and the third sub layer are equal to each other, and atomic percentages of germanium in the first sub layer, the second sub layer, and the third sub layer are equal to each.

8. The device of claim 1, wherein the second semiconductor region has a conduction band lower than conduction bands of the first semiconductor region and the third semiconductor region.

9. A device comprising:

a silicon substrate;

Shallow Trench Isolation (STI) regions extending into the silicon substrate;

a semiconductor fin protruding higher than top surfaces of the STI regions, wherein the semiconductor fin is between opposite portions of the STI regions;

a silicon germanium region contacting a top surface and sidewalls of the semiconductor fin, wherein the silicon germanium region comprises;

a first sub layer having a first n-type impurity concentration; and

a second sub layer over the first sub layer, wherein the second sub layer has a second n-type impurity concentration higher than the first n-type impurity concentration;

a gate dielectric over the silicon germanium region;

a gate electrode over the gate dielectric; and

a source region and a drain region on opposite sides of the gate dielectric and the gate electrode, wherein the source region and the drain region are n-type regions, and wherein the silicon germanium region extends from the source region and the drain region.

10. The device of claim 9, wherein the first sub layer is free from p-type impurities.

11. The device of claim 10 further comprising a third sub layer over the second sub layer, and the third sub layer is free from both n-type impurities and n-type impurities.

12. The device of claim 9, wherein the semiconductor fin is intrinsic.

13. The device of claim 9 further comprising an additional silicon germanium region located between and in contact with the STI regions, wherein the additional silicon germanium region is relaxed.

14. The device of claim 9 further comprising a silicon cap over the silicon germanium region, wherein the silicon cap is substantially free from germanium, and the silicon cap is intrinsic.

15. A device comprising:

a gate stack;

a source region and a drain region on opposite sides of the gate stack;

a silicon germanium region overlapped by the gate stack, and extending from the source region to the drain region, wherein the silicon germanium region comprises;

a first layer having a first n-type impurity concentration;

a second layer over the first layer, wherein the second layer has a second n-type impurity concentration; and

a third layer over the second layer, wherein the third layer has a third n-type impurity concentration, and the second n-type impurity concentration is higher than both the first n-type impurity concentration and the third n-type impurity concentration;

a gate dielectric over the silicon germanium region;

a gate electrode over the gate dielectric; and

a source region and a drain region on opposite sides of the gate dielectric and the gate electrode.

16. The device of claim 15, wherein the first layer and the third layer are substantially free from n-type impurities.

17. The device of claim 16, wherein the first layer and the third layer are further free from p-type impurities.

18. The device of claim 15 further comprising a silicon layer free from germanium between the third layer and the gate dielectric, wherein the silicon layer and the silicon germanium region extends from the source region to the drain region, and the silicon layer is undoped with p-type and n-type impurities.

19. The device of claim 15 further comprising:

isolation regions; and

a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the silicon germanium region is on a top surface and sidewalls of the semiconductor fin, and the semiconductor fin is undoped with p-type and n-type impurities.

20. The device of claim 15, wherein the first layer, the second layer, and the third layer have a same germanium atomic percentage.