FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH DIFFERENT GATE PROFILE AND METHOD FOR FORMING THE SAME

• US 20170352656A1
• Filed: 06/01/2016
• Published: 12/07/2017
• Est. Priority Date: 06/01/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUANG, Yi-Ching, CHIANG, Tsung-Yu, YANG, Ya-Wen
• Granted Patent: US 9,899,382 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 21/12 Protecting executable software
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: G06F 21/51 at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure. The first gate structure has a first top width in a direction that is parallel to the fin structure, the second gate structure has a second top width in a direction that is parallel to the fin structure, and the first top width is greater than the second top width.

Claims

1. A fin field effect transistor (FinFET) device structure, comprising:

a fin structure formed over a substrate;

an isolation structure formed over the substrate; and

a first gate structure and a second gate structure formed over the fin structure, wherein the first gate structure has a first top width in a direction that is parallel to the fin structure, the second gate structure has a second top width in a direction that is parallel to the fin structure, and the first top width is greater than the second top width, wherein a first angle is between a top surface of the first gate structure and a sidewall surface of the first gate structure, a second angle is between a top surface of the second gate structure and a sidewall surface of the second gate structure, and the second angle is greater than the first angle.

2. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein a ratio of the first top width to the second top width is in a range from about 1.2 to about 2.5.

3. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the first gate structure is a first conductivity type, and the second gate structure is a second conductivity type opposite to the first conductivity type.

4. The fin field effect transistor (FinFET) device structure as claimed in claim 3, wherein the first conductivity type gate structure is an N-type gate structure, and the second conductivity type gate structure is a P-type gate structure.

6. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the first gate structure has a trapezoid-shaped structure with a first bottom width, and the first top with is greater than the first bottom width.

7. The fin field effect transistor (FinFET) device structure as claimed in claim 1, further comprising:

an inter-layer dielectric (ILD) structure between the first gate structure and a second gate structure, wherein the ILD structure has a trapezoid-shaped structure.

8. The fin field effect transistor (FinFET) device structure as claimed in claim 7, wherein the ILD structure has a Ge-gradient concentration.

9. The fin field effect transistor (FinFET) device structure as claimed in claim 7, further comprising:

a contact etch stop layer (CESL) formed between ILD structure and the first gate structure, wherein the contact etch stop layer has sloped sidewalls.

10. The fin field effect transistor (FinFET) device structure as claimed in claim 7, wherein the ILD structure comprises an undoped portion and a doped portion, and a first sidewall of the undoped portion is not parallel to a sidewall of the doped portion.

5. (canceled)

11. A fin field effect transistor (FinFET) device structure, comprising:

a fin structure formed over a substrate;

an isolation structure formed over the substrate; and

a first gate structure and a second gate structure formed over the fin structure, wherein the first gate structure has a trapezoid-shaped structure, the second gate structure has a trapezoid-shaped structure, and a first angle is between a top surface of the first gate structure and a sidewall surface of the first gate structure, a second angle is between a top surface of the first gate structure and a sidewall surface of the second gate structure, and the second angle is greater than the first angle.

12. The fin field effect transistor (FinFET) device structure as claimed in claim 11, wherein the first gate structure is an N-type gate structure, and the second gate structure is a P-type gate structure.

13. The fin field effect transistor (FinFET) device structure as claimed in claim 11, further comprising:

an inter-layer dielectric (ILD) structure between the first gate structure and the second gate structure, wherein the ILD structure has a trapezoid-shaped structure.

14. The fin field effect transistor (FinFET) device structure as claimed in claim 11, wherein the ILD structure has a tapered width from a bottom portion to a top portion.

15. The fin field effect transistor (FinFET) device structure as claimed in claim 11, wherein the ILD structure has a Ge-gradient concentration.

16-20. -20. (canceled)

21. A fin field effect transistor (FinFET) device structure, comprising:

a fin structure formed over a substrate;

an isolation structure formed over the substrate;

a first gate structure and a second gate structure formed over the fin structure; and

an inter-layer dielectric (ILD) structure between the first gate structure and the second gate structure, wherein the ILD structure has a trapezoid-shaped structure, and the ILD structure comprises an undoped portion and a doped portion, and a first sidewall of the undoped portion is not parallel to a second sidewall of the doped portion.

23. The fin field effect transistor (FinFET) device structure as claimed in claim 21, further comprising:

a contact etch stop layer (CESL) formed between ILD structure and the first gate structure, wherein the contact etch stop layer has sloped sidewall surfaces.

24. The fin field effect transistor (FinFET) device structure as claimed in claim 21, wherein the ILD structure has a pair of sidewall surfaces, and the sidewall surfaces of the ILD structure taper gradually toward a top surface of the ILD structure.

25. The fin field effect transistor (FinFET) device structure as claimed in claim 21, wherein the first gate structure has a pair of sidewall surfaces, and the sidewall surfaces of the first gate structure taper gradually toward a bottom surface of the first gate structure.

22. (canceled)