VERTICAL FIELD EFFECT TRANSISTORS WITH BOTTOM SOURCE/DRAIN EPITAXY

• US 20170352742A1
• Filed: 06/02/2016
• Published: 12/07/2017
• Est. Priority Date: 06/02/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: CHENG, Kangguo, MIAO, Xin, XU, Wenyu, ZHANG, Chen
• Granted Patent: US 9,865,705 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

Claims

1. A method for fabricating a vertical fin field-effect-transistor, the method comprising:

forming a structure comprising a substrate, a first source/drain layer comprising a plurality of pillar structures, and a plurality of fins formed on and in contact with the plurality of pillar structures;

epitaxially growing a doped layer on the first source/drain layer in contact with the plurality of fins and the plurality of pillar structures;

forming a gate structure in contact with two or more fins in the plurality of fins, the gate structure comprising a dielectric layer and a gate layer;

forming a second source/drain layer on the gate structure; and

performing an anneal, the anneal driving dopants from the first source/drain layer and second source/drain layer into the two or more fins.

2. The method of claim 1, wherein forming the structure comprises:

etching through a channel layer and partially into the first source/drain layer, the etching forming the plurality of fins from the channel layer and the plurality of pillar structures.

3. The method of claim 1, further comprising:

after epitaxially growing the doped layer, forming a spacer layer in contact with the doped layer and the plurality of fins.

4. The method of claim 1, further comprising:

after forming the gate structure, forming a spacer layer in contact with the dielectric layer, the gate layer, and the two or more fins.

6. The method of claim 1, further comprising:

depositing a dielectric layer in contact with the spacer layer, the gate structure, and the second source/drain layer.

7. The method of claim 6, further comprising:

forming a first trench within the dielectric layer adjacent to the gate structure, the first trench exposing a portion of at least one pillar structure in the plurality of pillar structures and a portion of the doped layer;

forming at least a second trench within the dielectric layer on the gate structure, the second trench exposing a portion of the second source/drain layer;

forming a first contact within the first trench; and

forming a second contact within the second trench.

21. The method of claim 1, further comprising:

depositing a flowable oxide over the structure;

forming a mask in contact with a portion of the flowable oxide and over a subset of fins of the plurality of fins and a subset of pillar structures of the plurality of pillar structures;

forming one or more trenches within the flowable oxide to expose a portion of the substrate; and

depositing an isolation material within the one or more trenches.

22. The method of claim 1, further comprising:

etching one or more fins of the plurality of fins down to a spacer layer in contact with the doped layer and the plurality of fins.

23. The method of claim 22, wherein the etching is performed after a dialectic material for the dielectric layer has been deposited.

24. The method of claim 22, wherein the etching is performed after the second source/drain layer has been formed.

5. (canceled)

8-20. -20. (canceled)

25. A method for fabricating a vertical fin field-effect-transistor, the method comprising:

forming a structure comprising a substrate, a first source/drain layer comprising a plurality of pillar structures, and a plurality of fins formed on and in contact with the plurality of pillar structures;

epitaxially growing a doped layer on the first source/drain layer in contact with the plurality of fins and the plurality of pillar structures;

etching one or more fins of the plurality of fins, wherein a top surface of the one or more fins is below a top surface of remaining fins of the plurality of fins;

forming a gate structure in contact with two or more of the remaining fins in the plurality of fins, the gate structure comprising a dielectric layer and a gate layer; and

forming a second source/drain layer on the gate structure.

26. The method of claim 25, wherein forming the structure comprises:

etching through a channel layer and partially into the first source/drain layer, the etching forming the plurality of fins from the channel layer and the plurality of pillar structures.

27. The method of claim 25, further comprising:

after epitaxially growing the doped layer, forming a spacer layer in contact with the doped layer and the plurality of fins.

28. The method of claim 25, further comprising:

after forming the gate structure, forming a spacer layer in contact with the dielectric layer, the gate layer, and the two or more fins.

29. The method of claim 28, wherein the one or more fins are etched down to a top surface of the spacer layer.

30. The method of claim 25, further comprising:

performing an anneal, the anneal driving dopants from the first source/drain layer and second source/drain layer into the two or more fins.

31. The method of claim 25, further comprising:

depositing a dielectric layer in contact with the spacer layer, the gate structure, and the second source/drain layer.

32. The method of claim 31, further comprising:

forming a first trench within the dielectric layer adjacent to the gate structure, the first trench exposing a portion of at least one pillar structure in the plurality of pillar structures and a portion of the doped layer;

forming at least a second trench within the dielectric layer on the gate structure, the second trench exposing a portion of the second source/drain layer;

forming a first contact within the first trench; and

forming a second contact within the second trench.

33. The method of claim 25, wherein the one or more fins are etched after a dialectic material for the dielectric layer has been deposited.

34. The method of claim 25, further comprising:

depositing a flowable oxide over the structure;

forming a mask in contact with a portion of the flowable oxide and over a subset of fins of the plurality of fins and a subset of pillar structures of the plurality of pillar structures;

forming one or more trenches within the flowable oxide to expose a portion of the substrate; and

depositing an isolation material within the one or more trenches.