CREATION OF WIDE BAND GAP MATERIAL FOR INTEGRATION TO SOI THEREOF

• US 20170358608A1
• Filed: 07/31/2017
• Published: 12/14/2017
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: VERMA, Purakh Raj, ZHANG, Shaoqiang
• Granted Patent: US 10,192,886 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/2003 Nitride compounds

Abstract

Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

Claims

1. A device comprising:

a support substrate having first crystal orientation;

a trap rich layer disposed on the support substrate;

an insulator layer disposed over a top surface of the trap rich layer;

a top surface layer having second crystal orientation disposed on the insulator layer, wherein the support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions, and wherein the first and second device regions are separated by first isolation regions;

a transistor disposed in the top surface layer in the first device region; and

a wide band gap device disposed in the second device region, wherein the wide band gap device in the second device region is formed through a second isolation region in the second device region.

2. The device of claim 1 wherein the support substrate comprises a <

111>

oriented single crystal substrate and the top surface layer comprises a <

100>

oriented single crystal substrate.

3. The device of claim 1 wherein the trap rich layer comprises nano-crystal Si or wide band gap materials which comprise GaN, AlGaN, GaAs or SiC.

4. The device of claim 1 wherein the first isolation regions extend to a top surface of the insulator layer.

5. The device of claim 4 wherein the second isolation region has a greater width than the first isolation regions.

6. The device of claim 5 wherein the wide band gap device is isolated from the top surface layer by a portion of the second isolation region in the second device region.

7. The device of claim 1 wherein the second isolation region and the insulator layer are formed by the same material.

8. The device of claim 1 further comprising an etch stop layer over the top surface layer in the first and second device regions.

9. The device of claim 8 wherein the etch stop layer covers the transistor in the first device region.

10. The device of claim 8 further comprising an opening to expose the insulation layer and a portion of trap rich layer in the second device region.

11. The device of claim 10 further comprising a protective layer disposed in the second device region, wherein the protective layer covers sidewalls of the opening.

12. The device of claim 11 wherein the protective layer extends from a top surface of the top surface layer towards a top surface of the support substrate.

13. The device of claim 11 wherein the protective layer extends from a top surface of the top surface layer towards a top surface of the trap rich layer.

14. The device of claim 1 wherein the wide band gap device in the second device region comprises a High Electron Mobility Transistor (HEMT) or Hetero-junction Bipolar Transistor (HBT) device, wherein the HEMT or HBT device comprises an emitter and active layers.

15. The device of claim 14 further comprising a dielectric layer, contact plugs are disposed in the dielectric layer, the contact plugs extend to the emitter and the active layers of the HEMT or HBT device.

16. The device of claim 1 wherein the wide band gap device in the second device region comprises a gate and S/D regions.

17. The device of claim 16 further comprising a dielectric layer, contact plugs are disposed in the dielectric layer, the contact plugs extend to the gate and the S/D regions of the wide band gap device.

18. A device comprising:

a support substrate having first crystal orientation;

a trap rich layer disposed on the support substrate;

an insulator layer disposed over a top surface of the trap rich layer;

a top surface layer having second crystal orientation disposed on the insulator layer, wherein the support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions;

a transistor disposed in the top surface layer in the first device region; and

a wide band gap device disposed in the second device region, wherein the wide band gap device in the second device region is formed through a second isolation region in the second device region.

19. The device of claim 18 wherein the support substrate comprises a <

111>

oriented single crystal substrate and the top surface layer comprises a <

100>

oriented single crystal substrate.

20. The device of claim 18 wherein the wide band gap device in the second device region comprises a High Electron Mobility Transistor (HEMT) or Hetero-junction Bipolar Transistor (HBT) device.