STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE

• US 20170358681A1
• Filed: 08/28/2017
• Published: 12/14/2017
• Est. Priority Date: 05/20/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHANG, Che-Cheng, LIN, Chih-Han
• Granted Patent: US 10,431,687 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

Claims

1. A method for forming a semiconductor device structure, comprising:

forming a fin structure over a semiconductor substrate;

forming a gate stack over the semiconductor substrate to cover a portion of the fin structure; and

partially removing the gate stack such that the gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

2. The method for forming a semiconductor device structure as claimed in claim 1, further comprising replacing the gate stack with a metal gate stack.

3. The method for forming a semiconductor device structure as claimed in claim 2, further comprising forming a source/drain feature on the fin structure before replacing the gate stack with the metal gate stack.

4. The method for forming a semiconductor device structure as claimed in claim 1, wherein the partial removal of the gate stack includes in-situ performing multiple etching operations in a process chamber.

5. The method for forming a semiconductor device structure as claimed in claim 4, wherein gas mixtures used in the multiple etching operations are different from each other.

6. The method for forming a semiconductor device structure as claimed in claim 1, wherein the partially removing the gate stack forms a recess extending from a sidewall of the gate stack towards an inner portion of the gate stack and a sidewall of the fin structure.

7. The method for forming a semiconductor device structure as claimed in claim 1, further comprising:

epitaxially growing a feature on the fin structure adjacent the gate stack.

8. The method for forming a semiconductor device structure as claimed in claim 7, wherein the epitaxially growing the feature is performed prior to the partially removing the gate stack.

9. The method for forming a semiconductor device structure as claimed in claim 7, wherein the partially removing the gate stack includes a first etching process of a plasma etch.

10. The method for forming a semiconductor device structure as claimed in claim 9, wherein the partially removing the gate stack includes a second etching process after the first etching process, wherein the second etching process forms a polymer layer on the gate stack.

11. The method for forming a semiconductor device structure as claimed in claim 10, wherein the partially removing the gate stack further includes a third etching process after the second etching process, wherein the third etching process is a plasma etch.

12. A method of fabricating a semiconductor device structure, the method comprising:

providing a fin structure over a semiconductor substrate;

depositing a gate electrode layer covering a portion of the fin structure;

after depositing the gate electrode layer, etching a recess in the gate electrode layer, wherein the recess extends from a sidewall of the gate electrode towards an inner portion of the gate electrode and a sidewall of the fin structure; and

epitaxially growing a feature on the fin structure, wherein the recess is between the epitaxially grown feature and the gate stack.

13. The method of claim 12, wherein the etching the recess includes:

performing a first plasma etching process to form an etched gate stack; and

performing a second process after the first plasma etching process to form a protection film on the etched gate stack.

14. The method of claim 13, wherein the performing the first plasma etching process and the performing the second process are performed in-situ.

15. The method of claim 13, wherein the protection film is formed with a first thickness on a first region of the gate stack adjacent the fin structure and a second thickness on a second region of the gate stack spaced a distance from the fin structure, wherein the first thickness is less than the second thickness.

16. The method of claim 15, further comprising:

performing a third etching process after the second process, wherein the third etching process includes etching a larger amount of the gate stack at the first region than the second region.

17. A method for forming a semiconductor device structure, comprising:

forming a fin structure over a semiconductor substrate;

forming a gate electrode over the semiconductor substrate to cover a portion of the fin structure, wherein the gate electrode includes a first portion and a second portion, the second portion nearer a sidewall of the fin structure, wherein the second portion has a width equal to or greater than the first portion; and

after forming the gate stack, plasma etching a recess in the gate electrode, wherein the plasma etching reduces the width of the second portion such that it is less than the first portion.

18. The method of claim 17, wherein the plasma etching includes a step of depositing a protection layer onto the gate stack.

19. The method of claim 18, wherein the protection layer is a polymer.

20. The method of claim 18, wherein the protection layer has a first thickness on the second portion and a second thickness on the first portion, the second thickness being greater than the first thickness.