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WRITE BUFFER DESIGN FOR HIGH-LATENCY MEMORIES

  • US 20170364262A1
  • Filed: 06/16/2016
  • Published: 12/21/2017
  • Est. Priority Date: 06/16/2016
  • Status: Active Grant
First Claim
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1. A memory system, comprising:

  • a write buffer;

    a main memory having a higher latency than the write buffer;

    a memory controller coupled with the main memory and with the write buffer, wherein the memory controller is configured to;

    in response to a write request indicating first data for storing at a write address in the main memory, add a new write entry in the write buffer, wherein the new write entry includes the write address and the first data,in response to the write request, update a pointer of a previous write entry in the write buffer to point to the new write entry, andin response to a write-back instruction, traverse a plurality of write entries stored in the write buffer including the previous write entry and the new write entry, and write into the main memory second data of the previous write entry and the first data of the new write entry.

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