MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE DEVICE AND SIGNAL RECEIVING METHOD

• US 20170365328A1
• Filed: 05/10/2017
• Published: 12/21/2017
• Est. Priority Date: 06/20/2016
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Huang, Ming-Chien, Ma, Chia-Lung, Huang, Tzu-Chia
• Granted Patent: US 9,990,983 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 2207/10 Aspects relating to interfaces of memory device to external buses
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

Claims

1. A memory control circuit unit, configured to control a volatile memory, and the memory control circuit unit comprising:

a memory controller; and

a memory interface circuit, coupled to the memory controller,

wherein the memory interface circuit is configured to receive a first signal from the volatile memory,

wherein the memory interface circuit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit,

wherein a central value of the voltage range is not equal to a default voltage value,

wherein the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage,

wherein the memory interface circuit is further configured to generate an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

2. The memory control circuit unit according to claim 1, wherein the memory interface circuit comprises an impedance component configured to provide the internal impedance,

wherein a first terminal of the impedance component is coupled to a reception path of the first signal, wherein a second terminal of the impedance component is coupled to the supply voltage or the reference ground voltage.

3. The memory control circuit unit according to claim 2, wherein a third terminal of the impedance component is configured to receive an enabling signal, wherein the impedance component provides the internal impedance in response to the enabling signal.

4. The memory control circuit unit according to claim 3, wherein an enabling time of the enabling signal is positively correlated to a total number of bits sequentially transmitted through the first signal.

5. The memory control circuit unit according to claim 1, wherein the memory interface circuit is further configured to receive a second signal form the volatile memory before receiving the first signal,

wherein the memory interface circuit is further configured to perform a voltage division on the second signal so as to generate the internal reference voltage.

6. The memory control circuit unit according to claim 5, wherein the memory interface circuit is further configured to send a default read command sequence to instruct reading a default data of the volatile memory,

wherein the volatile memory is configured to generate the second signal according to the default read command sequence.

7. The memory control circuit unit according to claim 1, wherein the memory interface circuit comprises a comparison circuit,

wherein the comparison circuit is configured to compare the internal reference voltage with the voltage value of the first signal so as to generate the input signal.

8. The memory control circuit unit according to claim 1, wherein the volatile memory is configured to provide an external impedance,

wherein the voltage value of the first signal is further adjusted to the voltage range in response to the external impedance.

9. The memory control circuit unit according to claim 1, wherein the volatile memory comprises a Double Data Rate 4 Synchronous Dynamic Random Access Memory.

10. The memory control circuit unit according to claim 1, wherein the memory interface circuit comprises:

a first connection interface, configured to couple to the memory controller;

a second connection interface, configured to couple to the volatile memory; and

a reference voltage generator, coupled to the first connection interface and the second connection interface,

wherein the reference voltage generator is configured to detect the internal impedance through the first connection interface, detect an external impedance of the volatile memory through the second connection interface and generate the internal reference voltage according to a detection result.

11. The memory control circuit unit according to claim 10, wherein the reference voltage generator comprises:

a voltage detection circuit, configured to detect a first voltage of an impedance component in the memory interface circuit in response to the internal impedance and the external impedance,

wherein a voltage value of the first voltage is positively correlated to the voltage value of the supply voltage.

12. The memory control circuit unit according to claim 11, wherein the reference voltage generator further comprises:

a voltage division circuit, coupled to the voltage detection circuit and configured to perform a voltage division on a second voltage at an output terminal of the voltage detection circuit; and

a voltage output circuit, coupled to the voltage division circuit and configured to generate the internal reference voltage in response to a third voltage at an output terminal of the voltage division circuit.

13. A memory storage device, comprising:

a connection interface unit, configured to couple to a host system;

a rewritable non-volatile memory module;

a volatile memory;

a memory control circuit unit, coupled to the connection interface unit, the rewritable non-volatile memory module and the volatile memory,

wherein the memory control circuit unit is configured to receive a first signal from the volatile memory,

wherein the memory control circuit unit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory control circuit unit,

wherein a central value of the voltage range is not equal to a default voltage value,

wherein the default voltage value is one half a sum of a voltage value of a supply voltage of the memory control circuit unit and a voltage value of a reference ground voltage,

wherein the memory control circuit unit is further configured to generate an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

14. The memory storage device according to claim 13, wherein the memory control circuit unit comprises an impedance component configured to provide the internal impedance,

wherein a first terminal of the impedance component is coupled to a reception path of the first signal, wherein a second terminal of the impedance component is coupled to the supply voltage or the reference ground voltage.

15. The memory storage device according to claim 14, wherein a third terminal of the impedance component is configured to receive an enabling signal, wherein the impedance component provides the internal impedance in response to the enabling signal.

16. The memory storage device according to claim 15, wherein an enabling time of the enabling signal is positively correlated to a total number of bits sequentially transmitted through the first signal.

17. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to receive a second signal form the volatile memory before receiving the first signal,

wherein the memory control circuit unit is further configured to perform a voltage division on the second signal so as to generate the internal reference voltage.

18. The memory storage device according to claim 17, wherein the memory control circuit unit is further configured to send a default read command sequence to instruct reading a default data of the volatile memory,

wherein the volatile memory is configured to generate the second signal according to the default read command sequence.

19. The memory storage device according to claim 13, wherein the memory control circuit unit comprises a comparison circuit,

wherein the comparison circuit is further configured to compare the internal reference voltage with the voltage value of the first signal so as to generate the input signal.

20. The memory storage device according to claim 13, wherein the volatile memory is configured to provide an external impedance,

wherein the voltage value of the first signal is further adjusted to the voltage range in response to the external impedance.

21. The memory storage device according to claim 13, wherein the volatile memory comprises a Double Data Rate 4 Synchronous Dynamic Random Access Memory.

22. A signal receiving method for a memory storage device having a volatile memory, and the signal receiving method comprising:

receiving a first signal from the volatile memory by a memory interface circuit;

adjusting a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, wherein a central value of the voltage range is not equal to a default voltage value, wherein the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage; and

generating an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

23. The signal receiving method according to claim 22, further comprising:

providing the internal impedance by an impedance component of the memory interface circuit,

wherein a first terminal of the impedance component is coupled to a reception path of the first signal, wherein a second terminal of the impedance component is coupled to the supply voltage or the reference ground voltage.

24. The signal receiving method according to claim 23, further comprising:

receiving an enabling signal by a third terminal of the impedance component; and

providing the internal impedance by the impedance component in response to the enabling signal.

25. The signal receiving method according to claim 24, further comprising:

controlling an enabling time of the enabling signal, wherein the enabling time is positively correlated to a total number of bits sequentially transmitted through the first signal.

26. The signal receiving method according to claim 22, further comprising:

receiving a second signal form the volatile memory by the memory interface circuit before receiving the first signal; and

performing a voltage division on the second signal so as to generate the internal reference voltage.

27. The signal receiving method according to claim 26, further comprising:

sending a default read command sequence to instruct reading a default data of the volatile memory; and

generating the second signal by the volatile memory according to the default read command sequence.

28. The signal receiving method according to claim 22, wherein the step of generating the input signal according to the voltage correspondence between the first signal and the internal reference voltage comprises:

comparing the internal reference voltage with the voltage value of the first signal; and

generating the input signal according to a comparison result.

29. The signal receiving method according to claim 22, further comprising:

providing an external impedance by the volatile memory; and

adjusting the voltage value of the first signal to the voltage range in response to the external impedance.

30. The signal receiving method according to claim 22, wherein the volatile memory comprises a Double Data Rate 4 Synchronous Dynamic Random Access Memory.