DEVICES AND METHODS OF FORMING ASYMMETRIC LINE/SPACE WITH BARRIERLESS METALLIZATION

• US 20170365509A1
• Filed: 06/15/2016
• Published: 12/21/2017
• Est. Priority Date: 06/15/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: RYAN, Errol Todd, LICAUSI, Nicholas Vincent
• Granted Patent: US 10,008,408 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal

Abstract

Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width; damaging an inner surface of each trench of the set of trenches; etching the damaged material of the trenches removing the damaged material of the dielectric matrix; removing the hardmask; and metallizing the trenches by depositing a metal directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching. Also disclosed is an intermediate device formed by the method.

Claims

1. A method comprising:

obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width;

damaging an inner surface of each trench of the set of trenches;

etching the damaged material of the trenches removing the damaged material of the dielectric matrix;

removing the hardmask; and

metallizing the trenches by depositing a metal in the trenches directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching.

2. The method of claim 1, further comprising:

planarizing a top surface of the intermediate semiconductor device using chemical mechanical polishing.

3. The method of claim 1, wherein the hardmask covers an entirety of a top surface of each dielectric fin of the set of dielectric fins.

4. The method of claim 1, wherein the etching comprises exposure to dilute hydrofluoric acid.

5. The method of claim 4, wherein the etching and the removal of the hardmask occur simultaneously.

6. The method of claim 4, wherein the etching comprises a single exposure to the dilute hydrofluoric acid.

7. The method of claim 1, further comprising:

depositing a barrier layer on the inner surface of the trenches prior to the metallization.

8. The method of claim 1, wherein the dielectric matrix comprises one of SiCOH or pSiCOH.

9. The method of claim 1, wherein the metal comprises one of a group including:

Cu, Co, and Ru.

10. The method of claim 1, wherein the damaging comprises exposing the inner surface of the trenches to a plasma.

11. The method of claim 10, wherein the exposure comprises remote plasma exposure or direct plasma exposure.

12. The method of claim 10, wherein the plasma comprises one of a group including:

NH₃, O₂, and CO₂.

13. The method of claim 1, wherein the damaging comprises exposing the inner surface of the trenches to ozone.

14. The method of claim 1, wherein the damaging comprises exposing the inner surface of the trenches to a photolysis of a material via exposure to a broadband UV source and the material simultaneously.

15. The method of claim 14, wherein the material comprises one of a group including:

NH₃, O₂, and CO₂.

16. An intermediate device comprising:

a substrate;

a dielectric matrix;

a set of dielectric fins; and

a set of metallized trenches between the dielectric fins, the metallized trenches being wider than the dielectric fins, wherein the metallized trenches comprise a metal directly contacting the dielectric matrix without a liner or a barrier.

17. The device of claim 16, further comprising:

a barrier layer surrounding the set of metallized trenches.

18. A method comprising:

obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of different widths;

damaging an inner surface of each trench of the set of trenches;

etching the damaged material of the trenches removing the damaged material of the dielectric matrix;

removing the hardmask; and

metallizing the trenches by depositing a metal in the trenches directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching.

19. The method of claim 18, wherein the set of dielectric fins are wider than the set of trenches.

20. The method of claim 18, wherein the set of trenches is wider than the set of dielectric fins.