SEMICONDUCTOR DEVICE

• US 20170365604A1
• Filed: 06/02/2017
• Published: 12/21/2017
• Est. Priority Date: 06/21/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SUH, Dong-chan, PARK, Gi-gwan, KIM, Dong-woo, SHIN, Dong-suk
• Granted Patent: US 10,361,202 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Claims

1. A semiconductor device, comprising:

a substrate including a first region and a second region;

fin type active areas extending in a first direction away from the substrate, the fin type active areas being included in each of the first and second regions;

a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, each of the nanosheets having a channel region;

a gate extending over the fin type active areas in a second direction crossing the first direction, wherein the gate surrounds at least a portion of each of the nanosheets;

a gate dielectric layer interposed between the nanosheets and the gate;

first source and drain regions included in the first region, and second source and drain regions included in the second region, the first source and drain regions and the second source and drain regions being connected to the nanosheets and respectively including materials different from one another; and

insulating spacers interposed between the fin type active areas and the nanosheets, wherein

air spacers are interposed between the insulating spacers and the first source and drain regions in the first region.

2. The semiconductor device as claimed in claim 1, wherein

the gate includes a main gate portion on the nanosheets, the main gate portion having a first thickness, and a plurality of sub-gate portions between the nanosheets and the fin type active areas, the sub-gate portions having a second thickness less than the first thickness, and

the insulating spacers cover sidewalls of each of the sub-gate portions, and the gate dielectric layer is interposed between the insulating spacers and the sub-gate portions.

3. The semiconductor device as claimed in claim 2, wherein, in the second region, the second source and drain regions directly contact and completely cover side surfaces of sidewalls of the insulating spacers opposite the sub-gate portions.

4. The semiconductor device as claimed in claim 2, wherein a thickness of a lowest sub-gate portion among the plurality of sub-gate portions is greater than respective thicknesses of remaining sub-gate portions.

5. The semiconductor device as claimed in claim 2, wherein a volume of an air spacer between the insulating spacer covering sidewalls of the lowest sub-gate portion among the plurality of sub-gate portions and the first source and drain regions is different from volumes of the air spacers between the insulating spacers covering sidewalls of the remaining sub-gate portions and the first source and drain regions.

6. The semiconductor device as claimed in claim 5, wherein a vertical height of the insulating spacer covering the sidewalls of the lowest sub-gate portion among the plurality of sub-gate portions is different from vertical heights of the insulating spacers covering the sidewalls of the remaining sub-gate portions.

7. The semiconductor device as claimed in claim 1, wherein the first source and drain regions include a semiconductor material including germanium (Ge), and the second source and drain regions include a semiconductor material not including Ge.

8. The semiconductor device as claimed in claim 1, wherein, in the first source and drain regions, heights of the air spacers decrease in a direction perpendicular to a major surface of the substrate.

9. The semiconductor device as claimed in claim 1, wherein the air spacers extend from the nanosheets to the fin type active areas.

10. The semiconductor device as claimed in claim 1, wherein the air spacers project toward the insulating spacers.

11. A semiconductor device, comprising:

a substrate including active areas in each of first and second regions;

at least one nanosheet stack structure facing upper surfaces of the active areas and being spaced apart from the upper surfaces of the active areas, the at least one nanosheet stack structure including a plurality of nanosheets each having a channel region;

a gate extending over the active areas in a direction crossing the active areas, the gate covering the at least one nanosheet stack structure, wherein the gate includes a main gate portion disposed over the at least one nanosheet stack structure and a plurality of sub-gate portions disposed under each of the plurality of nanosheets;

a gate dielectric layer interposed between the at least one nanosheet stack structure and the gate;

first source and drain regions included in the first region, and second source and drain regions included in the second region, the first source and drain regions and the second source and drain regions being connected to the nanosheets;

a first insulating spacer disposed on the plurality of nanosheets, the first insulating spacer covering sidewalls of the gate; and

a plurality of second insulating spacers interposed between the sub-gate portions and the first source and drain regions in spaces between the upper surfaces of the active areas and the at least one nanosheet stack structure and spaces between the plurality of nanosheets in the first region and interposed between the sub-gate portions and the second source and drain regions in spaces between the upper surfaces of the active areas and the at least one nanosheet stack structure and the spaces between the plurality of nanosheets in the second region, wherein air spacers are interposed between the second insulating spacers and the first source and drain regions in the first region, and the second insulating spacers contact the second source and drain regions in the second region.

12. The semiconductor device as claimed in claim 11, wherein:

the air spacers are respectively disposed between the second insulating spacers and the first source and drain regions, and

volumes of the air spacers differ based on distances between the air spacers and a major surface of the substrate.

13. The semiconductor device as claimed in claim 11, wherein respective lengths of the sub-gate portions are substantially equal to length of the main gate portion.

14. The semiconductor device as claimed in claim 11, wherein the first source and drain regions include germanium (Ge) or silicon-germanium (SiGe), and the second source and drain regions include silicon (Si) or silicon carbide (SiC).

15. The semiconductor device as claimed in claim 11, wherein the second source and drain regions directly contact and cover side surfaces of sidewalls of the second insulating spacers opposite the sub-gate portions, and no air spacers are between the second insulating spacers and the second source and drain regions.

16. A semiconductor device, comprising:

a substrate including a first region and a second region adjacent to each other;

a first nanosheet stack structure in the first region, and a second nanosheet stack structure in the second region, the first and second nanosheet structures each including a lowermost nanosheet coplanar with one another, a metal or metal nitride conductive layer on the lowermost nanosheet, and a second nanosheet on the conductive layer, the second nanosheet having a width greater than that of the conductive layer such that the second nanosheet overhangs the conductive layer to form a recess;

first source and drain regions disposed on opposite sides of the first nanosheet stack structure;

second source and drain regions disposed on opposite sides of the second nanosheet stack structure;

insulating spacers disposed in the recesses of the first and second nanosheet stack structures, the insulating spacers in the recesses of the second nanosheet stack structure contacting the second source and drain regions, and the insulating spacers in the recesses of the first nanosheet stack structure being separated from the first source and drain regions by an air gap.

17. The semiconductor device as claimed in claim 16, wherein the first region is a PMOS region, and the second region is an NMOS region.

18. The semiconductor device as claimed in claim 17, wherein the air gap has at least one side having an angle corresponding to a (111) crystal plane of material of the first source and drain regions.

19. The semiconductor device as claimed in claim 18, wherein the insulating spacer disposed in the recesses of the first nanosheet structure is exposed to air in the air gap.

20. The semiconductor device as claimed in claim 16, wherein the insulating spacers of the first and second nanosheet stack structures are formed of a same material, and the material of the first source and drain regions is different from the material of the second source and drain regions.