Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle

• US 20170365607A1
• Filed: 08/11/2017
• Published: 12/21/2017
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 9,960,166 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

Claims

1-21. -21. (canceled)

22. An integrated circuit comprising:

an array of semiconductor memory cells comprising at least two semiconductor memory cells, wherein each said semiconductor memory cell includes;

a transistor comprising a source region, a first floating body region, a drain region, and a gate, and a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region,

wherein;

a state of said memory cell is stored in said first floating body region,

said first floating body region and said second floating body region are common,

said silicon controlled rectifier device maintains a state of said memory cell,

said transistor is usable to access said memory cell, and

wherein said anode region is commonly connected to at least two of said memory cells; and

a control circuit configured to provide electrical signals to said anode region, wherein when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, application of electrical signals via said control circuit maintains said first memory cell in said first state and said second memory cell in said second state.

23. The integrated circuit of claim 22, wherein said electrical signals to said anode region are constant voltage biases.

24. The integrated circuit of claim 22, wherein said electrical signals to said anode region are periodic pulses of voltage.

25. The integrated circuit of claim 22, wherein said transistor is formed in a fin structure.

26. The integrated circuit of claim 22, wherein said anode region is commonly connected to all of said semiconductor memory cells in said array.

27. The integrated circuit of claim 22, wherein said anode region is segmented to allow independent control of bias applied on a selected portion of said memory array.

28. An integrated circuit comprising:

an array of semiconductor memory cells comprising at least two semiconductor memory cells, wherein each said semiconductor memory cell includes;

a transistor comprising a source region, a first floating body region, a drain region, and a gate, and a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region;

wherein;

a state of said semiconductor memory cell is stored in said first floating body region,

said first floating body region and said second floating body region are common,

said silicon controlled rectifier device maintains a state of said memory cell,

said transistor is usable to access said memory cell; and

wherein said anode region is commonly connected to at least two of said memory cells;

a first control circuit configured to provide electrical signals to said anode region to maintain a state of said semiconductor memory cell;

a second control circuit configured to perform read operations of said semiconductor memory cells; and

wherein states of said semiconductor memory cells are maintained upon repeated read operations.

29. The integrated circuit of claim 28, wherein said electrical signals to said anode region are constant voltage biases.

30. The integrated circuit of claim 28, wherein said electrical signals to said anode region are periodic pulses of voltage.

31. The integrated circuit of claim 28, wherein said transistor is formed in a fin structure.

32. The integrated circuit of claim 28, wherein said anode region is commonly connected to all of said semiconductor memory cells in said array.

33. The integrated circuit of claim 28, wherein said anode region is segmented to allow independent control of bias applied on a selected portion of said memory array.

34. An integrated circuit comprising:

an array of semiconductor memory cells comprising at least two semiconductor memory cells, wherein each said semiconductor memory cell includes;

a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and

a substrate region positioned below said buried layer region;

a first control circuit configured to provide electrical signals to said substrate region to maintain states of said semiconductor memory cells;

a second control circuit configured to perform read operations of said semiconductor memory cells; and

wherein states of said semiconductor memory cells are maintained upon repeated read operations.

35. The integrated circuit of claim 34, wherein said electrical signals to said anode region are constant voltage biases.

36. The integrated circuit of claim 34, wherein said electrical signals to said anode region are periodic pulses of voltage.

37. The integrated circuit of claim 34, wherein said transistor is formed in a fin structure.

38. The integrated circuit of claim 34, wherein said substrate region is commonly connected to all of said cells in said array.

39. The integrated circuit of claim 34, wherein said substrate region is segmented to allow independent control of bias applied on a selected portion of said memory array.