FLOATING GATE MEMORY CELLS IN VERTICAL MEMORY

• US 20170365615A1
• Filed: 08/30/2017
• Published: 12/21/2017
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Dennison, Charles H., Goda, Akira, Hopkins, John, Simsek-Ege, Fatma Arzum, Parat, Krishna K.
• Granted Patent: US 9,991,273 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Claims

1. A method of forming a memory array, comprising:

forming a control gate tier between first and second vertically spaced dielectric tiers;

forming an opening extending through the first and second dielectric tiers;

forming a recess in the control gate tier, the recess extending at least partially around the opening;

forming a charge blocking structure within the recess and adjacent the control gate, wherein the charge blocking structure comprises a dielectric material and a barrier material; and

forming a floating gate within the recess and on the opposite side of the charge blocking structure from the control gate, wherein a first portion of the floating gate contacts each of the first and second dielectric tiers;

wherein a substantially vertical portion of the barrier material is between the control gate and the floating gate; and

wherein a first substantially horizontal portion of the charge blocking structure extends laterally between the first tier of dielectric material and a second portion of the floating gate, and wherein a second substantially horizontal portion of the charge blocking structure extends laterally between the second tier of dielectric material and the second portion of the floating gate.

2. The method of claim 1, wherein the second portion of the floating gate includes a protrusion extending from the first portion of the floating gate and in the direction of the control gate, the protrusion having a smaller vertical dimension than the first portion of the floating gate.

3. The method of claim 2, wherein a thickness of the substantially vertical portion of the charge blocking structure is greater than a thickness of the first substantially horizontal portion of the charge blocking structure and is greater than a thickness of the second substantially horizontal portion of the charge blocking structure.

4. The method of claim 1, wherein a length of the floating gate between the tiers of dielectric material is substantially equal to a length of the control gate between the tiers of dielectric material.

5. The method of claim 1, wherein the barrier material comprises a layer of nitride.

6. The method of claim 1, wherein the charge blocking structure comprises first and second layers of oxide.

7. The method of claim 2, wherein the charge blocking structure comprises a first oxide contacting the control gate and a second oxide contacting the floating gate, and wherein the barrier material is positioned between the first oxide and the second oxide.

8. The method of claim 7, wherein at least a portion of the charge blocking structure wraps around the protrusion.

9. The method of claim 7, wherein the second oxide completely separates the layer of nitride from the protrusion of the floating gate.

10. The method of claim 7, wherein the floating gate is in contact with the barrier material and the second oxide.

11. The method of claim 8, wherein the portion of the charge blocking structure that wraps around the protrusion includes a portion of the barrier material.

12. A method of forming a memory array, comprising:

forming multiple vertically spaced dielectric tiers;

forming control gate tiers extending between respective vertically adjacent dielectric tiers;

forming a vertical string of charge storage devices, comprising,

forming an opening extending through the multiple dielectric tiers and multiple control gate tiers;

in the control gate tiers, forming a recess extending at least partially around the opening;

In the recesses, forming a charge blocking structure adjacent the control gate, wherein the charge blocking structure comprises a dielectric material and a barrier material; and

within the recesses, forming a floating gate on the opposite side of the charge blocking structure from the control gate, wherein a first portion of the floating gate contacts each of the vertically adjacent dielectric tiers;

wherein a substantially vertical portion of the barrier material is between the control gate and the floating gate; and

wherein a first substantially horizontal portion of the charge blocking structure extends laterally between the first tier of dielectric material and a second portion of the floating gate, and wherein a second substantially horizontal portion of the charge blocking structure extends laterally between the second tier of dielectric material and the second portion of the floating gate;

forming a dielectric within the opening and over the surfaces of the floating gates; and

forming a conductive pillar extending vertically through the multiple dielectric tiers and multiple control gate tiers.

13. The method of claim 12, wherein the second portion of the floating gates includes a protrusion extending from the first portion of the floating gate and in the direction of the control gate, the protrusion having a smaller vertical dimension than the first portion of the floating gate.

14. The method of claim 13, wherein the charge blocking structure comprises a first oxide contacting the control gate and a second oxide contacting the floating gate, and wherein the barrier material is positioned between the first oxide and the second oxide.

15. The method of claim 14, wherein the second oxide completely separates the layer of nitride from the protrusion of the floating gate.

16. The method of claim 15, wherein the floating gate is in contact with the barrier material and the second oxide.

17. The method of claim 13, wherein the portion of the charge blocking structure that wraps around the protrusion includes a portion of the barrier material.

18. An apparatus including a vertical string of memory cells, wherein a memory cell of the vertical string of memory cells comprises:

a control gate between a first tier of dielectric material and a second tier of dielectric material;

a floating gate between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a first portion, and a second port and including a protrusion extending in the direction of the control gate, the protrusion having a smaller vertical dimension than the first portion of the floating gate; and

a charge blocking structure between the floating gate and the control gate, wherein the charge blocking structure comprises a barrier film and first and second oxides,

wherein a substantially vertical portion of the charge blocking structure is between the control gate and the floating gate,

wherein a first substantially horizontal portion of the charge blocking structure extends laterally, separating the floating gate from the first tier of dielectric material, and

wherein a second substantially horizontal portion of the charge blocking structure extends laterally, separating the floating gate from the second tier of dielectric material.

19. The apparatus of claim 19, wherein the first and second substantially horizontal portions of the charge blocking structure include a portion of the barrier film extending around at least a portion of the protrusion of the floating gate.

20. The apparatus of claim 19 wherein the floating gate is separated from the barrier film by one of the first and second oxides.

21. The apparatus of claim 19 wherein the floating gate is in contact with both the barrier film and one of the first and second oxides.