ASPECT RATIO TRAPPING IN CHANNEL LAST PROCESS

• US 20170365692A1
• Filed: 06/15/2016
• Published: 12/21/2017
• Est. Priority Date: 06/15/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi, Yeh, Chun-chen
• Granted Patent: US 10,249,736 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02428 Structure
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.

Claims

1. A method of forming the fin structure comprising:

forming a replacement gate structure is formed on a channel region of the at least one replacement fin structure;

forming an encapsulating dielectric on the substrate and the at least one replacement gate structure, wherein the encapsulating dielectric encapsulates the replacement fin structure and a portion of the replacement gate structure is exposed;

etching an exposed portion of the replacement gate structure to provide an opening through the encapsulating dielectric to the replacement fin structure;

etching the replacement fin structure selectively to the encapsulating dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric that exposes a growth surface of the substrate; and

epitaxially growing functional fin structures of a second semiconductor material on the growth surface of the substrate substantially filling the fin opening.

2. The method of claim 1, wherein the fin opening includes a substrate trench portion having a width greater than a fin body portion of said fin opening.

3. The method of claim 2, wherein a difference in width between said substrate trench portion and said fin body portion provides for aspect ratio trapping of defects formed during said epitaxially growing said functional fin structures.

4. The method of claim 3, wherein the aspect ratio trapping provides that a portion of the second semiconductor material in the substrate trench portion includes defects, and a portion of the second semiconductor material formed in the fin body portion of said fin opening is substantially free of defects.

5. The method of claim 4, wherein a defect density of the second semiconductor material in the substrate trench portion ranges from 1 defect/cm² to 133 10¹¹ defects/cm².

6. The method of claim 5, wherein a defect density of the second semiconductor material in the fin body portion ranges from 0 defects/cm² to 1×

10¹⁰ defects/cm².

7. The method of claim 1, wherein the first semiconductor material is a type IV semiconductor selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe) and combinations thereof, and the second semiconductor material is a type III-V semiconductor material selected from the group consisting of indium phosphide (InP), (InGaAs) and combinations thereof.

8. A method of forming a semiconductor device comprising:

forming a replacement gate structure on a channel region of the at least one replacement fin structure;

forming an encapsulating dielectric that encapsulates the replacement fin structure leaving a portion of the replacement gate structure exposed;

etching the portion of the replacement gate structure that is exposed to provide an opening through the encapsulating dielectric to the replacement fin structure;

etching the replacement fin structure selectively to the encapsulating dielectric to provide a fin opening;

functional fin structures of a second semiconductor material are epitaxially grown on a growth surface of the substrate exposed by the fin opening; and

replacing a remaining portion of the replacement gate structure with a functional gate structure.

9. The method of claim 8 further comprising forming source and drain regions on source and drain portions of the functional fin structure.

10. The method of claim 8, wherein the fin opening includes a substrate trench portion having a width greater than a fin body portion of said fin opening.

11. The method of claim 10, wherein a difference in width between said substrate trench portion and said fin body portion provides for aspect ratio trapping of defects formed during said epitaxially growing said functional fin structures.

12. The method of claim 11, wherein the aspect ratio trapping provides that a portion of the second semiconductor material in the substrate trench portion includes defects, and a portion of the second semiconductor material formed in the fin body portion of said fin opening is substantially free of defects.

13. The method of claim 12, wherein a defect density of the second semiconductor material in the substrate trench portion ranges from 1 defects/cm² to 1×

10¹¹ defects/cm².

14. The method of claim 13, wherein a defect density of the second semiconductor material in the fin body portion ranges from 0 defects/cm² to 1×

10¹⁰ defects/cm².

15. The method of claim 8, wherein the first semiconductor material is a type IV semiconductor selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe) and combinations thereof, and the second semiconductor material is a type III-V semiconductor material selected from the group consisting of indium phosphide (InP), indium gallium arsenic (InGaAs) and combinations thereof.

16. A semiconductor device comprising:

a substrate of a type IV semiconductor material having a trench present therein;

a plurality of type III-V fin structures joined by an epitaxial base portion that is present within the trench of the type IV semiconductor material, wherein the epitaxial base portion in epitaxial relationship with the trench of the type IV semiconductor substrate;

a gate structure present on a channel region portion of the type III-V fin structures; and

source and drain regions present on source and drain region portions of the type III-V fin structures.

17. The semiconductor device of claim 16, wherein the first semiconductor material is a type IV semiconductor selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe) and combinations thereof.

18. The semiconductor device of claim 16, wherein the second semiconductor material is a type III-V semiconductor material selected from the group consisting of indium phosphide (InP), indium gallium arsenic (InGaAs) and combinations thereof.

19. The semiconductor device of claim 16, wherein the type III-V fin structures have a body portion with a defect density that ranges from 0 defects/cm² to 1×

10¹⁰ defects/cm².

20. The semiconductor device of claim 16, wherein the type III-V fin structures have a substrate trench portion with a defect density that ranges from 1 defects/cm² to 1×

10¹¹ defects/cm².