ANALOG FRACTIONAL-N PHASE-LOCKED LOOP
First Claim
1. An analog fractional-N phase-locked loop, comprising:
- an oscillator loop having;
a reference input, a feedback input, and a loop output, anda fractional feedback divider configured to divide signals on the loop output by a divisor, wherein output of the fractional feedback divider is fed back to the feedback input; and
a compensation circuit coupled to one of the reference input and the feedback input, the compensation circuit configured to apply a time delay to the one of the reference input and the feedback input to compensate for delay introduced by the fractional feedback divider.
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Abstract
An analog fractional-N phase-locked loop includes an oscillator loop having a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor. Output of the fractional feedback divider is fed back to the feedback input. A compensation circuit is coupled to, and configured to apply a time delay to, the reference input or the feedback input, to compensate for delay introduced by the fractional feedback divider. The compensation circuit may be a digital-to-time converter configured to convert a digital delay signal into the time delay. The digital-to-time converter may be coupled to the reference input to delay signals to match feedback delay introduced by the fractional feedback divider, or to the feedback input to subtract the time delay to cancel feedback delay introduced by the fractional feedback divider.
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Citations
22 Claims
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1. An analog fractional-N phase-locked loop, comprising:
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an oscillator loop having; a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor, wherein output of the fractional feedback divider is fed back to the feedback input; and a compensation circuit coupled to one of the reference input and the feedback input, the compensation circuit configured to apply a time delay to the one of the reference input and the feedback input to compensate for delay introduced by the fractional feedback divider. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of operating an analog fractional-N phase-locked loop, including an oscillator loop having a reference input, a feedback input, and a loop output, and having a fractional feedback divider configured to divide signals on the loop output by a divisor, wherein output of the fractional feedback divider is fed back to the feedback input, the method comprising:
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measuring delay introduced by the fractional feedback divider; and compensating for the feedback delay introduced by the fractional feedback divider by applying a time delay to the one of the reference input and the feedback input. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A compensation circuit for an analog fractional-N phase-locked loop including an oscillator loop having a reference input, a feedback input, a loop filter and a loop output, and having a fractional feedback divider in a feedback position between the loop output and the feedback input, the compensation circuit comprising:
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circuitry that is configured to measure delay introduced by the fractional feedback divider; and circuitry that is configured to compensate for the feedback delay introduced by the fractional feedback divider by applying a time delay to the one of the reference input and the feedback input. - View Dependent Claims (20, 21, 22)
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Specification