METHODS FOR SPECIFYING PROCESSOR ARCHITECTURES FOR PROGRAMMABLE INTEGRATED CIRCUITS

• US 20170371836A1
• Filed: 06/23/2016
• Published: 12/28/2017
• Est. Priority Date: 06/23/2016
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Granted Patent: US 10,110,233 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns

Abstract

A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.

Claims

1. A method of using processor generator tools implemented on computing equipment to generate a processor on a programmable integrated circuit, the method comprising:

presenting a user with an opportunity to specify desired processor parameters;

receiving the processor parameters from the user;

analyzing the received processor parameters to determine whether a viable processor can be generated; and

in response to determining that a viable processor can be generated based on the received processor parameters, generating the processor for the programmable integrated circuit.

2. The method of claim 1, further comprising:

in response to determining that the received processor parameters are not viable, providing alternative processor parameters.

3. The method of claim 1, wherein generating the processor for the programmable integrated circuit comprises generating a reduced instruction set computing (RISC) processor for the programmable integrated circuit.

4. The method of claim 1, wherein receiving the processor parameters comprises receiving a data word size for a given data path in the processor.

5. The method of claim 1, wherein receiving the processor parameters comprises receiving different data word sizes for multiple data paths in the processor.

6. The method of claim 1, wherein receiving the processor parameters comprises receiving an instruction word size for the processor.

7. The method of claim 1, wherein receiving the processor parameters comprises receiving a number of registers for the processor.

8. The method of claim 1, wherein receiving the processor parameters comprises receiving a number of interrupts that is supported by the processor.

9. The method of claim 1, wherein receiving the processor parameters comprises receiving a set of instructions for the processor.

10. The method of claim 9, further comprising:

in response to receiving the set of instructions, using the processor generator tools to determine which functional units are required on the programmable integrated circuit.

11. The method of claim 10, further comprising:

in response to receiving the set of instructions, using the processor generator tools to determine which of the functional units are implemented using soft logic and hard logic on the programmable integrated circuit.

12. A method for using processor generator tools implemented on computing equipment to generate a processor on a programmable integrated circuit, the method comprising:

generating the processor with a plurality of processor components;

providing suggested pipeline settings for each of the processor components in the processor; and

inserting additional pipeline stages into the processor based on the suggested pipeline settings.

13. The method of claim 12, further comprising:

presenting a user of the processor generator tools with an opportunity to choose from among the suggested pipeline settings.

14. The method of claim 13, further comprising:

verifying that the pipeline settings chosen by the user pass legality check.

15. The method of claim 12, further comprising:

implementing the plurality of processor components using soft logic and hard logic on the programmable integrated circuit;

inserting a first number of pipeline stages in a first component in the plurality of processor components that has been implemented in the soft logic; and

inserting a second number of pipeline stages in a second component in the plurality of processor components that has been implemented in the hard logic, wherein the first number is greater than the second number.

16. A method for using processor generator tools implemented on computing equipment to generate a processor on a programmable integrated circuit, the method comprising:

generating the processor with a plurality of data paths;

analyzing each of the plurality of data paths to determine whether a hazard is present;

in response to determining that the processor exhibits a hazard, providing an option to resolve the hazard; and

modifying the processor so that the modified processor is free from the hazard.

17. The method of claim 16, wherein analyzing each of the plurality of data paths comprises analyzing each of the plurality of data paths to determine whether a structural hazard is present in the processor.

18. The method of claim 17, wherein providing the option comprises providing an option selected from the group consisting of:

an option to add ports to a register file in the processor;

an option to specify a priority resolution scheme for conflicting operations;

an option to partition a destination register in the processor;

an option to temporarily stall the processor;

an option to temporarily store values in a shadow register; and

an option to increase the number of identical multicycle operations in the processor.

19. The method of claim 16, wherein analyzing each of the plurality of data paths comprises analyzing each of the plurality of data paths to determine whether a data hazard is present in the processor.

20. The method of claim 19, wherein providing the option comprises providing an option selected from the group consisting of:

an option to manage the data hazard in software;

an option to implement hardware interlocking to stall the top of a processor pipeline; and

an option to specify a level of forwarding for each data path in the plurality of data paths.