MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS

• US 20170372769A1
• Filed: 07/10/2017
• Published: 12/28/2017
• Est. Priority Date: 12/21/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kizer, Jade M., Doraiswamy, Sivakumar, Lau, Benedict
• Granted Patent: US 9,905,286 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

Claims

1. (canceled)

2. An integrated circuit (IC) memory controller comprising:

a strobe signal pin to receive a strobe signal;

a delay circuit coupled to the strobe signal pin to apply a delay to the strobe signal, the delay circuit to output a delayed strobe signal;

a mask circuit having an input to receive the delayed strobe signal, the mask circuit to generate a masked timing signal based on the delayed strobe signal; and

a sampler coupled to the mask circuit to sample read data based on the masked timing signal.

3. The IC memory controller according to claim 2, wherein:

the mask circuit generates the masked timing signal based on the delayed strobe signal and a read enable signal.

4. The IC memory controller according to claim 2, wherein the IC memory controller is embodied as a dynamic random access memory (DRAM) controller.

5. The IC memory controller according to claim 2, wherein the delay circuit includes one or more delay elements.

6. The IC memory controller according to claim 5, wherein the one or more delay elements are configured such that the applied delay is based on a relative timing difference between the strobe signal and a corresponding data signal.

7. The IC memory controller according to claim 2, further comprising:

a buffer coupled to the sampler to receive sampled read data and provide the sampled read data to a requesting device.

8. The IC memory controller according to claim 2, wherein the strobe signal is associated with a first clock domain, and wherein the mask circuit further comprises:

latching circuitry to, in response to an edge transition of the strobe signal that indicates the start of a valid region of the strobe signal, latch the masked timing signal into the clock domain of the strobe signal.

9. A method of operation in a memory controller, the method comprising:

receiving a strobe signal;

applying a delay to the strobe signal to generate a delayed strobe signal;

generating a masked timing signal based on the delayed strobe signal; and

sampling read data based on the masked timing signal.

10. The method according to claim 9, wherein generating the masked timing signal includes:

generating the masked timing signal based on the delayed strobe signal and a read enable signal.

11. The method according to claim 9, wherein the IC memory controller operates in accordance with a dynamic random access memory (DRAM) protocol.

12. The method according to claim 9, wherein applying a delay comprises:

applying a delay based on a relative timing difference between the strobe signal and a corresponding data signal.

13. The method according to claim 9, wherein the sampling generates sampled read data, and wherein the method further comprises:

buffering the sampled read data.

14. The method according to claim 9, wherein the strobe signal is associated with a first clock domain, and wherein the generating a masked timing signal further comprises:

latching the masked timing signal into the clock domain of the strobe signal in response to an edge transition of the strobe signal that indicates the start of a valid region of the strobe signal.

15. An integrated circuit (IC) chip comprising:

memory control circuitry including

a strobe signal pin to receive a strobe signal;

a delay circuit coupled to the strobe signal pin to apply a delay to the strobe signal, the delay circuit to output a delayed strobe signal;

a mask circuit having an input to receive the delayed strobe signal, the mask circuit to generate a masked timing signal based on the delayed strobe signal; and

a sampler coupled to the mask circuit to sample read data based on the masked timing signal.

16. The IC chip according to claim 15, wherein the memory control circuitry comprises dynamic random access memory (DRAM) memory control circuitry.

17. The IC chip according to claim 15, wherein the mask circuit is operative to mask at least a portion of the strobe signal in generating the masked timing signal.

18. The IC chip according to claim 17, wherein the mask circuit generates the masked timing signal based on the delayed strobe signal and a read enable signal.

19. The IC chip according to claim 15, further comprising:

a buffer coupled to the sampler to receive sampled read data and provide the sampled read data to a requesting device.

20. The IC chip according to claim 15, wherein the delay circuitry is configured such that the applied delay is based on a relative timing difference between the strobe signal and a corresponding data signal.

21. The IC chip according to claim 15, wherein the strobe signal is associated with a first clock domain, and wherein the mask circuit further comprises:

latching circuitry to, in response to an edge transition of the strobe signal that indicates the start of a valid region of the strobe signal, latch the masked timing signal into the clock domain of the strobe signal.