Reduced Substrate Effects in Monolithically Integrated RF Circuits

• US 20170372945A1
• Filed: 06/27/2016
• Published: 12/28/2017
• Est. Priority Date: 06/27/2016
• Status: Active Grant

• Current Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Original Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Inventors: Howard, David J., DeBar, Michael J., Hurwitz, Paul D.
• Granted Patent: US 9,966,301 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3731 Ceramic materials or glass H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence

Abstract

A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle substrate, the device layer having at least one semiconductor device, forming a front side glass on a front side of the semiconductor wafer, and partially removing the handle substrate from a back side of the semiconductor wafer. The method also includes removing a portion of the semiconductor wafer from an outer perimeter thereof, either by sawing an edge trim trench through the handle substrate, the device layer and into the front side glass to form a ring, and removing the ring on the outer perimeter of the semiconductor wafer, or by edge grinding the outer perimeter of the semiconductor wafer. The method further includes completely removing the handle substrate.

Claims

1. A method of forming a semiconductor structure, said method comprising:

forming a semiconductor wafer having a device layer situated over a handle substrate, said device layer having at least one semiconductor device;

forming a front side glass on a front side of said semiconductor wafer;

partially removing said handle substrate from a back side of said semiconductor wafer;

removing an outer perimeter of said semiconductor wafer.

2. The method of claim 1 wherein said front side glass is coupled to said front side of said semiconductor wafer by oxide fusion bonding.

5. The method of claim 1 wherein said removing said outer perimeter of said semiconductor wafer comprises edge grinding.

6. The method of claim 1 further comprising completely removing said handle substrate by etching.

7. The method of claim 1 further comprising forming at least one pad opening extending from said back side of said semiconductor wafer to a contact pad.

8. The method of claim 1 wherein said handle substrate comprises a silicon on insulator substrate.

9. The method of claim 1 further comprising forming a thermally conductive but electrically isolating layer on said back side of said semiconductor wafer.

10. The method of claim 9 wherein said thermally conductive but electrically isolating layer replaces said handle substrate so as to substantially eliminate parasitic capacitance in said semiconductor structure.

11. The method of claim 9 wherein said thermally conductive but electrically isolating layer is configured to dissipate heat from said at least one semiconductor device.

12. The method of claim 9 wherein said thermally conductive but electrically isolating layer is selected from the group consisting of aluminum nitride, beryllium oxide, and aluminum oxide.

13. The method of claim 9 wherein said thermally conductive but electrically isolating layer is thermally coupled to said at least one semiconductor device situated in said device layer.

14. The method of claim 9 wherein said thermally conductive but electrically isolating layer has a coefficient of thermal expansion that is closely matched with that of said device layer.

15. The method of claim 1 wherein said at least one semiconductor device comprises at least one of a complementary-metal-oxide-semiconductor (CMOS) device and a bipolar complementary-metal-oxide-semiconductor (BiCMOS) device.

16. The method of claim 1 wherein said semiconductor structure comprises an oxide layer between said front side glass and said semiconductor wafer.

17. The method of claim 1 wherein said at least one semiconductor device is electrically coupled to a contact pad on said front side of said semiconductor wafer.

18. The method of claim 1 wherein said semiconductor wafer comprises a contact pad in a dielectric layer over said device layer.

19. The method of claim 1 wherein said device layer comprises silicon or silicon germanium.

20. The method of claim 1 wherein said semiconductor wafer comprises an integrated passive device (IPD).

21. The method of claim 1 wherein said removing said outer perimeter of said semiconductor wafer comprises dry etching.

3-4. -4. (canceled)