FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE
First Claim
1. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:
- a doped region formed on a substrate;
a bottom source/drain contact formed on at least a portion of the doped region, wherein the doped region has one or more interfacial features that increases the surface area of the interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface.
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Accused Products
Abstract
A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.
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Citations
20 Claims
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1. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:
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a doped region formed on a substrate; a bottom source/drain contact formed on at least a portion of the doped region, wherein the doped region has one or more interfacial features that increases the surface area of the interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:
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a doped region formed on a substrate; a bottom source/drain contact formed on at least a portion of the doped region and electrically coupled to the doped region, wherein the doped region has one or more doped extensions that extend from the surface of the doped region into the bottom source/drain contact that increases the surface area of the interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:
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a doped region formed on a substrate; a bottom source/drain contact formed on at least a portion of the doped region and electrically coupled to the doped region, wherein the doped region has one or more recesses that extend into the surface of the doped region that increases the surface area of the interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification