FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE

• US 20170373162A1
• Filed: 06/01/2017
• Published: 12/28/2017
• Est. Priority Date: 06/24/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Miao, Xin, Xu, Wenyu, Zhang, Chen
• Granted Patent: US 10,431,659 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

Claims

1. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

a doped region formed on a substrate;

a bottom source/drain contact formed on at least a portion of the doped region, wherein the doped region has one or more interfacial features that increases the surface area of the interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface.

2. The vertical finFET of claim 1, wherein the doped region and the bottom source/drain contact are electrically coupled together.

3. The vertical finFET of claim 1, further comprising a gate structure formed on one or more vertical fins on the same doped region as the bottom source/drain contact.

4. The vertical finFET of claim 1, further comprising a top source/drain on at least one of the plurality of vertical fins, and a top source/drain contact formed on the top source/drain.

5. The vertical finFET of claim 1, wherein the one or more features that increases the surface area of the interface includes one or more doped extensions that extend from the surface of the doped region into the bottom source/drain contact.

6. The vertical finFET of claim 1, wherein the one or more features that increases the surface area of the interface includes one or more recesses that extend into the surface of the doped region.

7. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

a doped region formed on a substrate;

a bottom source/drain contact formed on at least a portion of the doped region and electrically coupled to the doped region, wherein the doped region has one or more doped extensions that extend from the surface of the doped region into the bottom source/drain contact that increases the surface area of the interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface.

8. The vertical finFET of claim 7, wherein the one or more doped extensions have a height in the range of about 10 nm to about 40 nm.

9. The vertical finFET of claim 8, wherein the doped region and one or more doped extensions include n-type dopants.

10. The vertical finFET of claim 8, wherein the doped region and one or more doped extensions include p-type dopants.

11. The vertical finFET of claim 8, wherein the bottom source/drain contact is tungsten, copper, titanium, aluminum, or combinations thereof.

12. The vertical finFET of claim 11, further comprising a gate structure formed on one or more vertical fins on the same doped region as the bottom source/drain contact.

13. The vertical finFET of claim 12, further comprising a top source/drain on the one or more vertical fins, and a top source/drain contact formed on the top source/drain.

14. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

a doped region formed on a substrate;

a bottom source/drain contact formed on at least a portion of the doped region and electrically coupled to the doped region, wherein the doped region has one or more recesses that extend into the surface of the doped region that increases the surface area of the interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface.

15. The vertical finFET of claim 14, wherein the one or more recesses do not extend all the way through the doped region.

16. The vertical finFET of claim 14, wherein the one or more recesses have a depth in the range of about 10 nm to about 40 nm.

17. The vertical finFET of claim 16, wherein the one or more recesses have a width in the range of about 6 nm to about 20 nm, and a length in the range of about 100 nm to about 1000 nm.

18. The vertical finFET of claim 17, wherein the bottom source/drain contact is tungsten, copper, titanium, aluminum, or combinations thereof, and the bottom source/drain contact fills the recesses.

19. The vertical finFET of claim 18, further comprising a gate structure formed on one or more vertical fins on the same doped region as the bottom source/drain contact.

20. The vertical finFET of claim 19, further comprising a top spacer layer on the gate structure, and a top source/drain on the one or more vertical fins, and a top source/drain contact formed on the top source/drain.