×

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE

  • US 20170373162A1
  • Filed: 06/01/2017
  • Published: 12/28/2017
  • Est. Priority Date: 06/24/2016
  • Status: Active Grant
First Claim
Patent Images

1. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

  • a doped region formed on a substrate;

    a bottom source/drain contact formed on at least a portion of the doped region, wherein the doped region has one or more interfacial features that increases the surface area of the interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×