VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR WITH PRECISE GATE LENGTH DEFINITION

• US 20170373166A1
• Filed: 06/28/2016
• Published: 12/28/2017
• Est. Priority Date: 06/28/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bergendahl, Marc A., Cheng, Kangguo, Lie, Fee Li, Miller, Eric R., Sporre, John R., Teehan, Sean
• Granted Patent: US 10,014,391 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.

Claims

1-10. -10. (canceled)

11. A method of forming a gate stack for a semiconductor device, the method comprising:

forming a vertical fin on a substrate, the vertical fin having an upper portion and a bottom portion, wherein the upper portion of the vertical fin has a recessed portion on sides of the upper portion; and

forming the gate stack in the recessed portion of the upper portion of the vertical fin, such that the gate stack is on the sides of the upper portion but not above the upper portion of the vertical fin.

12. The method of claim 11, further comprising forming a bottom spacer on top of the substrate and on the bottom portion of the vertical fin.

13. The method of claim 11, wherein a first hard mask layer is formed on top of the vertical fin, such that the gate stack is covered by the first hard mask layer.

14. The method of claim 13, wherein a second hard mask layer is formed on top of the first hard mask layer.

15. The method of claim 14, wherein a combined width of the upper portion of the vertical fin and the gate stack are about a same as a width of the second hard mask layer.

16. The method of claim 13, wherein the first hard mask layer has a width about a same as the upper portion of the vertical fin.

17. The method of claim 14, wherein the first and second hard mask layers are different materials.

18. The method of claim 14, wherein a spacer layer is formed on the vertical fin, the gate stack, the first hard mask layer, and a second hard mask layer.

19. The method of claim 14, wherein the first hard mask layer includes an oxide material, and the second hard mask layer includes a nitride material.

20. A method of forming a gate stack for a semiconductor device, the method comprising:

forming a vertical fin on a substrate, the vertical fin having an upper portion and a bottom portion;

forming a recessed portion in the upper portion of the vertical fin such that the recessed portion is on sides of the upper portion; and

forming the gate stack in the recessed portion of the upper portion of the vertical fin, such that the gate stack is on the sides of the upper portion but not above the upper portion of the vertical fin, wherein a gate length is predefined by the recessed portion.