SEARCHABLE HOT CONTENT CACHE

• US 20180004668A1
• Filed: 06/30/2016
• Published: 01/04/2018
• Est. Priority Date: 06/30/2016
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: AZIZI, Omid J., SOLOMATNIKOV, Alexandre Y., FIROOZSHAHIAN, Amin, STEVENSON, John P., MADDURY, Mahesh
• Application Number:
  US15/199,587
• Publication Number:
  US 20180004668A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/311 In host system
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0641 De-duplication techniques
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A searchable hot content cache stores frequently accessed data values in accordance with embodiments. In one embodiment, a circuit includes interface circuitry to receive memory requests from a processor. The circuit includes hardware logic to determine that a number of the memory requests that is to access a value meets or exceeds a threshold. The circuit includes a storage array to store the value in an entry based on a determination that the number meets or exceeds the threshold. In response to receipt of a memory request from the processor to access the same value at a memory address, the hardware logic is to map the memory address to the entry of the storage array.

Claims

1. A circuit comprising:

interface circuitry to receive memory requests from a processor;

hardware logic to determine that a number of the memory requests that are to access a value meets or exceeds a threshold; and

a storage array to store the value in an entry based on a determination that the number meets or exceeds the threshold;

wherein, in response to receipt of a memory request from the processor to access the value at a memory address, the hardware logic is to map the memory address to the entry of the storage array.

2. The circuit of claim 1, wherein:

the hardware logic is to further update a reference count for the entry to indicate a number of memory addresses mapped to the entry.

3. The circuit of claim 2, wherein:

in response to the map of the memory address to the entry, the hardware logic is to increment the reference count; and

in response to detection of a subsequent request to write a different value to the memory address, the hardware logic is to decrement the reference count.

4. The circuit of claim 1, further comprising:

a second storage array to store the memory address and an identifier for the entry of the storage array.

5. The circuit of claim 4, wherein:

the memory request comprises a read request; and

wherein the hardware logic to map the memory address to the entry is to read the value from the entry of the storage array.

6. The circuit of claim 5, wherein:

in response to receipt of the read request, the hardware logic is to determine that the memory address is in the second storage array;

wherein the hardware logic is to further read the identifier associated with the memory address in the second storage array; and

wherein the hardware logic is to read the value from the entry of the storage array based on the identifier.

7. The circuit of claim 4, wherein:

the memory request comprises a write request; and

wherein the hardware logic to map the memory address to the entry of the storage array is to, store, in the second storage array, the memory address and the identifier for the entry.

8. The circuit of claim 7, wherein:

in response to receipt of the write request, the hardware logic is to search for the value in the storage array; and

wherein the hardware logic is to map the memory address to the entry of the storage array based on a determination that the value is stored in the entry.

9. The circuit of claim 8, wherein:

the hardware logic to search for the value in the storage array is to;

determine a signature of the searched for value;

compare the signature of the searched for value with signatures stored in the storage array; and

in response to a matching signature, compare the searched for value with a value in the storage array corresponding to the matching signature.

10. The circuit of claim 1, wherein:

the hardware logic to determine that the number meets or exceeds the threshold is to;

track values within a window of requests; and

determine the value was requested more than once within the window of requests.

11. The circuit of claim 1, wherein:

the hardware logic to determine that the number meets or exceeds the threshold is to;

track values within a window of time; and

determine the value was requested more than once within the window of time.

13. The circuit of claim 1, further comprising:

a buffer to store signatures of values to be written by write requests within a window;

wherein the hardware logic is to compare the signatures in the buffer to determine whether the number meets or exceeds the threshold.

14. The circuit of claim 13, wherein:

the buffer is to store identifiers for entries of the storage array to which read requests within the window are redirected to;

wherein the hardware logic is to compare the identifiers in the buffer to determine whether the number meets or exceeds the threshold.

15. The circuit of claim 2, wherein:

the hardware logic to determine that the number meets or exceeds the threshold is to;

track the reference count of the value in an entry of the storage array; and

determine the reference count meets or exceeds a threshold value.

16. The circuit of claim 1, wherein:

in response to a determination that a given value is not stored in the storage array, the interface circuitry is to send a given memory request that is to access the given value to searchable memory logic to search for the given value in a searchable memory.

17. A system comprising:

a processor; and

a circuit communicatively coupled with the processor, the circuit comprising;

interface circuitry to receive memory requests from the processor;

hardware logic to determine that a number of the memory requests that is to access a value meets or exceeds a threshold; and

a storage array to store the value in an entry based on a determination that the number meets or exceeds the threshold;

wherein, in response to receipt of a memory request from the processor to access the value at a memory address, the hardware logic is to map the memory address to the entry of the storage array.

18. The system of claim 17, further comprising:

any of a display communicatively coupled to the processor, a network interface communicatively coupled to the processor, or a battery coupled to provide power to the system.

19. A method comprising:

receiving memory requests from a processor;

determining that a number of the memory requests that are to access a value meets or exceeds a threshold; and

storing the value in an entry of a storage array based on a determination that the number meets or exceeds the threshold;

wherein, in response to receiving a memory request from the processor to access the value at a memory address, mapping the memory address to the entry of the storage array.

20. The method of claim 19, further comprising:

updating a reference count for the entry to indicate a number of memory addresses mapped to the entry.