VARIATION-AWARE DESIGN ANALYSIS

• US 20180004880A1
• Filed: 06/29/2016
• Published: 01/04/2018
• Est. Priority Date: 06/29/2016
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Sattiraju, Sri Harsha
• Granted Patent: US 10,204,200 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A microprocessor evaluation system evaluates a microprocessor circuit by using analysis-specific custom corners that are derived specifically for the analysis of interest. Circuit parameters specific to the analysis of interest are applied to a proposed design to derive the custom corners, which will trigger violations more accurately than corners selected using traditional methods. The custom corners could also be reused in between design phases to reduce redesign simulation time. Local process parameters could be taken into account using worst-case local parameter offsets to detect violations in a far more accurate manner than using generic guard-band budgets.

Claims

1. A system that evaluates designs for a microprocessor circuit, comprising a non-transitory computer-readable medium storing instructions that, when executed by a computer processor, cause the computer processor to perform the steps of:

receiving a proposed design for the microprocessor circuit;

selecting a first analysis of interest from a set of analyses of interest that evaluates values of a first microprocessor measurement of interest;

selecting a first set of circuit parameters from a set of representative circuit parameters having analysis-specific stimuli as a function of the first analysis of interest and the proposed design;

applying the first set of circuit parameters to the proposed design to construct a first analysis-specific simulation model;

deriving a first set of analysis-specific custom corners for the proposed design as a function of the first analysis-specific simulation model; and

simulating the first analysis-specific simulation model as a function of the first set of analysis-specific custom corners to derive a first set of worst-case values for the first microprocessor measurement of interest.

2. The system of claim 1, wherein the non-transitory computer-readable medium further stores instructions that, when executed by the computer processor, cause the computer processor to perform the steps of:

selecting a second analysis of interest from the set of analyses of interest that evaluates values of a second microprocessor measurement of interest, wherein the second microprocessor measurement of interest is different from the first microprocessor measurement of interest;

selecting a second set of circuit parameters from the set of representative circuit parameters as a function of the second analysis of interest and the proposed design;

applying the second set of circuit parameters to the proposed design to construct a second analysis-specific simulation model;

deriving a second set of analysis-specific custom corners for the proposed design as a function of the second analysis of interest; and

simulating the second analysis-specific simulation model as a function of the second set of analysis-specific custom corners to derive a second set of worst-case values for the second microprocessor measurement of interest.

3. The system of claim 1, wherein the first analysis of interest is selected from the group consisting of:

an analysis of set up time values;

an analysis of hold time values;

an analysis of voltage leakage values;

an analysis of writability values;

an analysis of charge-sharing values;

an analysis of leakage power values;

an analysis of dynamic power values; and

an analysis of noise margin values.

4. The system of claim 1, wherein the first set of circuit parameters comprises a first design topology for the proposed design and a second design topology for the proposed design.

5. The system of claim 1, wherein the non-transitory computer-readable medium further stores instructions that, when executed by the computer processor, cause the computer processor to perform the steps of:

simulating the first analysis-specific simulation model as a function of the first set of analysis-specific custom corners while varying local process variation parameters to produce a set of local process variation results and;

deriving worst-case local process variation offsets as a function of the set of local process variation results.

6. The system of claim 5, wherein the non-transitory computer-readable medium further stores instructions that, when executed by the computer processor, cause the computer processor to add at least one of the worst-case local process variation offsets to a violation threshold for the first microprocessor measurement of interest.

7. The system of claim 5, wherein the non-transitory computer-readable medium further stores instructions that, when executed by the computer processor, cause the computer processor to add at least one of the worst-case local process variation offsets to the first set of worst-case values for the first microprocessor measurement of interest.

8. A method of evaluating designs for a microprocessor circuit, the method comprising:

receiving a proposed design for the microprocessor circuit;

receiving a first analysis of interest that evaluates values of a first microprocessor measurement of interest;

identifying a first set of circuit parameters having analysis-specific simuli as a function of the first analysis of interest and the proposed design;

producing first analysis-specific simulation model as a function of the first set of circuit parameters;

deriving a first set of analysis-specific custom corners for the proposed design as a function of the first analysis-specific simulation model; and

simulating the first analysis-specific simulation model as a function of the first set of analysis-specific custom corners to derive a first set of worst-case values for the first microprocessor measurement of interest.

9. The method of claim 8, wherein the step of deriving the first set of analysis-specific custom corners comprises performing statistical circuit simulations of the first analysis-specific simulation model to obtain analysis-specific simulated measurement data.

10. The method of claim 9, wherein the step of deriving the first set of analysis-specific custom corners comprises fitting a Weibull distribution to the analysis-specific simulated measurement data.

11. The method of claim 10, wherein the step of deriving the first set of analysis-specific custom corners further comprises transforming the Weibull distribution to a transformed Gaussian distribution.

12. The method of claim 11, wherein the step of deriving the first set of analysis-specific custom corners further comprises inputting the transformed Gaussian distribution to a joint probability distribution set to achieve a target joint sigma level.

13. The method of claim 9, wherein the statistical circuit simulations vary a first set of global process parameters between each statistical circuit simulation.

14. The method of claim 13, further comprising:

simulating the first analysis-specific simulation model as a function of the first set of analysis-specific custom corners while varying local process variation parameters to produce a set of local process variation results and;

deriving worst-case local process variation offsets as a function of the set of local process variation results.

15. The method of claim 14, further comprising adding at least one of the worst-case local process variation offsets to a violation threshold for the first microprocessor measurement of interest.

16. A computer system that evaluates designs for a microprocessor circuit, the computer system comprising:

a user interface programmed to;

receive a proposed design for the microprocessor circuit, and

receive a selection of a first analysis of interest from a set of analyses of interest that evaluates values of a first microprocessor measurement of interest; and

a computer processor programmed to;

select a first set of circuit parameters from a set of representative circuit parameters having analysis-specific stimuli as a function of the first analysis of interest and the proposed design,

apply the first set of circuit parameters to the proposed design to construct a first analysis-specific simulation model,

derive a first set of analysis-specific custom corners for the proposed design as a function of the first analysis-specific simulation model, and

simulate the first analysis-specific simulation model as a function of the first set of analysis-specific custom corners to derive a first set of worst-case values for the first microprocessor measurement of interest.

17. The computer system of claim 16, wherein the computer processor is further programmed to:

evaluate the first set of worst-case values against a set of allowed limits for the first microprocessor measurement of interest, and

transmit a notification of a violation when at least one of the first set of worst-case values violates at least one of the set of allowed limits.

18. The computer system of claim 17, wherein the computer processor is further programmed to transmit an instruction to redesign the proposed design to overcome the violation.

19. The computer system of claim 18, wherein the computer processor is further programmed to:

receive a redesign of the microprocessor circuit,

apply the first set of circuit parameters to the redesign to construct a second analysis-specific simulation model, and

simulate a second set of worst-case empirical models of the microprocessor circuit as a function of the first set of analysis-specific custom corners and the second analysis-specific simulation model.

20. The computer system of claim 17, wherein the computer processor is further programmed to:

simulate the first analysis-specific simulation model while varying global process parameters and local process parameters to produce a golden set of empirical models,

evaluate the golden set of empirical models against the set of allowed limits for the first microprocessor measurement of interest, and

transmit a notification to waive the violation when none of the golden set of empirical models violates any of the set of allowed limits for the first microprocessor measurement of interest.