MEMORY DEVICE

• US 20180005698A1
• Filed: 06/30/2017
• Published: 01/04/2018
• Est. Priority Date: 07/01/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: UENO, Koki, SHIINO, Yasuhiro, KANEDA, Asuka
• Granted Patent: US 10,109,353 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.

Claims

1. A memory device comprising:

a plurality of memory cell transistors;

a word line electrically connected to gates of the memory cell transistors; and

a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification, wherein

the different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range, and

during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.

2. The memory device according to claim 1, wherein

during the program verification, the control circuit applies a first verification voltage to the word line when performing verification of the programming to the first threshold voltage range, and a second verification voltage to the word line when performing verification of the programming to the second threshold voltage range, the second verification voltage being higher than the first verification voltage.

3. The memory device according to claim 2, wherein the control circuit sets the second verification voltage in accordance with the number of loops required to complete programming to the first threshold voltage range.

4. The memory device according to claim 1, wherein the different threshold voltage ranges do not overlap and each of the first and second verification voltages are between two adjacent threshold voltage ranges.

5. The memory device according to claim 4, wherein the first verification voltage is between first and second threshold voltage ranges, and the second verification voltage is between the second threshold voltage range and a third threshold voltage range.

6. The memory device according to claim 1, wherein

the memory cell transistors hold n-bit data, where n is a natural number, and

the different threshold voltage ranges include 2ⁿ−

1 different threshold voltage ranges.

7. The memory device according to claim 1, wherein completion of the programming to the first threshold voltage range is achieved when threshold voltages of all the memory cell transistors that are targeted for programming to the first threshold voltage range are in the first threshold voltage range.

8. A memory device comprising:

a plurality of memory cell transistors;

a word line electrically connected to gates of the memory cell transistors; and

a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification, wherein

the different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range, and

during the program verification, the control circuit applies a first verification voltage to the word line when performing verification of the programming to the first threshold voltage range, and a second verification voltage to the word line when performing verification of the programming to the second threshold voltage range, the second verification voltage being higher than the first verification voltage and the control circuit setting the second verification voltage in accordance with a number of loops required to complete programming to the first threshold voltage range.

9. The memory device according to claim 8, wherein the different threshold voltage ranges do not overlap and each of the first and second verification voltages are between two adjacent threshold voltage ranges.

10. The memory device according to claim 9, wherein the first verification voltage is between first and second threshold voltage ranges, and the second verification voltage is between the second threshold voltage range and a third threshold voltage range.

11. The memory device according to claim 8, wherein

the memory cell transistors holds n-bit data, where n is a natural number, and

the different threshold voltage ranges include 2ⁿ−

1 different threshold voltage ranges.

12. The memory device according to claim 8, wherein completion of the programming to the first threshold voltage range is achieved when threshold voltages of all the memory cell transistors that are targeted for programming to the first threshold voltage range are in the first threshold voltage range.

13. A method for programming memory cell transistors of a memory device to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification, the method comprising:

during the program operation, applying a program voltage to a word line that is connected to gates of the memory cell transistors, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.

14. The method according to claim 13, wherein

during the program verification, the control circuit applies a first verification voltage to the word line when performing verification of the programming to the first threshold voltage range, and a second verification voltage to the word line when performing verification of the programming to the second threshold voltage range, the second verification voltage being higher than the first verification voltage.

15. The method according to claim 14, further comprising:

setting the second verification voltage in accordance with the number of loops required to complete programming to the first threshold voltage range.

16. The method according to claim 13, wherein the different threshold voltage ranges do not overlap and each of the first and second verification voltages are between two adjacent threshold voltage ranges.

17. The method according to claim 16, wherein the first verification voltage is between first and second threshold voltage ranges, and the second verification voltage is between the second threshold voltage range and a third threshold voltage range.

18. The method according to claim 13, wherein

the memory cell transistors hold n-bit data, where n is a natural number, and

the different threshold voltage ranges include 2ⁿ−

1 different threshold voltage ranges.

19. The method according to claim 13, wherein completion of the programming to the first threshold voltage range is achieved when threshold voltages of the memory cell transistors that are targeted for programming to the first threshold voltage range are in the first threshold voltage range.