LONG CHANNEL AND SHORT CHANNEL VERTICAL FET CO-INTEGRATION FOR VERTICAL FET VTFET

• US 20180006025A1
• Filed: 06/30/2016
• Published: 01/04/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hook, Terence B., Li, Baozhen, Peterson, Kirk David, Wang, Junli
• Granted Patent: US 11,251,179 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.

Claims

1-7. -7. (canceled)

8. A semiconductor chip, comprising:

a short channel device comprising a vertical FET (Field-Effect Transistor); and

a long channel device comprising a second vertical FET integrated with the short channel device,

wherein the long channel device comprises a series connection of a plurality of short channel devices, and

wherein the short channel and the long channel devices are co-integrated on a same chip.

9. The semiconductor chip according to claim 8 being a monolithic chip, wherein long channel and short channel devices form vertically stacked field effect transistors (FET).

10. The semiconductor chip according claim 8, wherein the long channel device comprises a plurality of series of fins between spacers and gate regions, and

wherein the short channel device comprises a fin through the spacer and the gate regions.

11. The semiconductor chip according claim 8, further comprising at least two vertical fins that are formed with bottom portions connected in the long channel device.

12. The semiconductor chip according claim 8, further comprising:

a plurality of contacts formed on a source-drain region for the long channel device and the short channel device,

wherein the plurality of contacts are formed to connect a top surface of the source-drain region for series connection of the short channel devices in the long channel device.

13. The semiconductor chip according to claim 8, further comprising of:

a single silicon substrate for both the long channel device and the short channel device; and

physically separate gates formed on the substrate.

14. The semiconductor chip according to claim 8, further comprising of a well formed and defining a bottom source-drain regions for the short and long channel devices.

15. The semiconductor according to claim 14, further comprising a bottom spacer on the well for the short and long channel devices.

16. The semiconductor chip according to claim 15, further comprising of a gate formed on the bottom spacer for the long and short channel devices.

17. The semiconductor chip according to claim 16, further comprising:

a top spacer for the long and short channel devices;

top drain and source regions formed on the top spacer; and

metal contacts connecting a plurality of drain-source regions in series.

18. The semiconductor chip according to claim 8, further comprising:

a plurality of fins formed in the long channel device;

top drain and source regions formed on each of the plurality of fins above the top spacer; and

metal contacts connecting a least two of the drain and source regions.

19. A semiconductor device, comprising:

a short channel device being vertically formed;

a long channel device being vertically formed and co-integrated with the short channel device on a same chip;

wherein the long channel device comprises;

a well;

a plurality of vertical fins formed over the well;

source-drain regions formed over a top surface of the plurality of fins; and

a plurality of metal contacts connecting at least two of the plurality of fins.

20. The semiconductor device according to claim 19, further comprising a plurality of sets of gates formed on a substrate, each set of gates being physically separated by a dielectric material,

wherein the short channel and the long channel devices have a same gate length.

21. A semiconductor device on a single chip, the semiconductor comprising:

a shallow trench isolation (STI) region formed for a short channel device and a long channel device in a substrate;

at least two vertical fins connected in the long channel device; and

contacts formed on a source-drain regions for the long channel device and the short channel device,

wherein the contacts connect a top surface of the source-drain region for a series FET (Field-Effect Transistor) connection for the long channel device.

22. The semiconductor device according to claim 21, further comprising:

a plurality of gates physically separated by a dielectric material on the substrate,

wherein the substrate comprises a silicon substrate for the both the long channel device and the short channel device.

23. The semiconductor device according to claim 22, wherein the at least two vertical tins are formed from the substrate by patterning.

24. The semiconductor device according to claim 23, further comprising a well defining a bottom source-drain region for the short and long channel devices.

25. The semiconductor device according to claim 23, further comprising a bottom spacer connected to the well for the short and long channel devices.

26. The semiconductor device according to claim 25, further comprising a gate formed on the bottom spacer for the long and short channel devices;

and

a top spacer formed for the long and short channel devices.

27. The semiconductor device according to claim 26, further comprising:

a series of the long channel devices with the gate comprising a thick oxide layer connected to a high voltage source in a planar layout with a shared gate contact, the high voltage source having a greater voltage than a low voltage source, the thick oxide layer having a greater thickness than a thin oxide layer; and

a series of the long channel devices with the gate comprising the thin oxide layer connected to low voltage source for analog implementation.