DISPLAY DEVICE

• US 20180011355A1
• Filed: 02/03/2016
• Published: 01/11/2018
• Est. Priority Date: 02/12/2015
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: MIYAKE, Hiroyuki, KANEYASU, Makoto
• Granted Patent: US 10,539,839 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/133602 Direct backlight
• CPC Class Codes: G02F 1/1343 Electrodes reflective electrodes G02F1/133553
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09F 9/30 in which the desired character or characters are formed by combining individual elements panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00
• CPC Class Codes: G09G 2300/0439 Pixel structures
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film. The signal line intersects with the scan line, the first electrode is electrically connected to the signal line, the first electrode has a region overlapping with the scan line, the second electrode faces the first electrode, the third electrode faces the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is provided between the scan line and the first electrode to the third electrode.

Claims

1. A display device comprising:

a signal line;

a scan line;

a first electrode;

a second electrode;

a third electrode;

a first pixel electrode;

a second pixel electrode; and

a semiconductor film,

wherein the signal line intersects with the scan line,

wherein the first electrode is electrically connected to the signal line,

wherein the first electrode includes a region overlapping with the scan line,

wherein the second electrode faces the first electrode,

wherein the third electrode faces the first electrode,

wherein the first pixel electrode is electrically connected to the second electrode,

wherein the second pixel electrode is electrically connected to the third electrode,

wherein the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and

wherein the semiconductor film is positioned between the scan line and the first electrode to the third electrode.

2. The display device according to claim 1, comprising a gate insulating film, a first transistor, and a second transistor,

wherein the gate insulating film is positioned between the scan line and the semiconductor film,

wherein the first transistor comprises the scan line, the gate insulating film, the semiconductor film, the first electrode, and the second electrode, and

wherein the second transistor comprises the scan line, the gate insulating film, the semiconductor film, the first electrode, and the third electrode.

3. The display device according to claim 1, comprising a first capacitor wiring and a second capacitor wiring,

wherein the first capacitor wiring is electrically connected to the first pixel electrode,

wherein a second capacitor wiring is electrically connected to the second pixel electrode,

wherein the signal line comprises a region overlapping with a region between the first pixel electrode and the second pixel electrode, and

wherein the signal line does not comprise a region overlapping with the first capacitor wiring and the second capacitor wiring.

4. The display device according to claim 3,

wherein the first electrode is positioned between the second electrode and the third electrode in a top surface shape.

5. The display device according to claim 1,

wherein the semiconductor film comprises an oxide comprising In, M (M is aluminum, gallium, yttrium, or tin), and Zn.

6. The display device according to claim 5,

wherein the semiconductor film comprises a first semiconductor film and a second semiconductor film comprising a region overlapping with the first semiconductor film, and

wherein the first semiconductor film comprises an oxide with a composition in which an atomic proportion of In is higher than an atomic proportion ofM by a larger difference than in a composition of an oxide contained in the second semiconductor film.