STREAM REFERENCE REGISTER WITH DOUBLE VECTOR AND DUAL SINGLE VECTOR OPERATING MODES
First Claim
1. A digital signal processor comprising:
- an instruction memory storing instructions each specifying a data processing operation and at least one data operand field;
an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand;
at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register;
a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine includinga first stream head register storing a data element of said stream next to be used, anda second stream head register storing a data element of said stream next to be used following said data stored in said first stream head register; and
wherein said instruction decoder is operable todecode an instruction having a predetermined first stream read coding to supply said data stored in said first stream head register to said corresponding functional unit, anddecode an instruction having a predetermined second stream read coding to supply said data stored in said second stream head register to said corresponding functional unit.
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Accused Products
Abstract
A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.
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Citations
146 Claims
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1. A digital signal processor comprising:
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an instruction memory storing instructions each specifying a data processing operation and at least one data operand field; an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand; at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register; a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including a first stream head register storing a data element of said stream next to be used, and a second stream head register storing a data element of said stream next to be used following said data stored in said first stream head register; and wherein said instruction decoder is operable to decode an instruction having a predetermined first stream read coding to supply said data stored in said first stream head register to said corresponding functional unit, and decode an instruction having a predetermined second stream read coding to supply said data stored in said second stream head register to said corresponding functional unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. A digital signal processor comprising:
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an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, said at least one instruction including a double width instruction; an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand; at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register, said at least one functional unit including at least one functional unit operable upon double width data in response to a double width instruction; a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including a first stream head register storing a data element of said stream next to be used, and a second stream head register storing a data element of said stream next to be used following said data stored in said first stream head register; and wherein said instruction decoder is operable to decode an instruction having a predetermined double width stream read coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data. - View Dependent Claims (54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100)
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101. A digital signal processor comprising:
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an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, said instructions including at least one single width instruction and at least one double width instruction, said instructions each including at least one data operand field specifying at least one operand; an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand; at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register, said at least one functional unit including at least one functional unit operable upon double width data in response to a double width instruction; a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including a first stream head register storing a data element of said stream next to be used, and a second stream head register storing a data element of said stream next to be used following said data stored in said first stream head register; and wherein said instruction decoder is operable to decode a single width instruction having a data operand field having one of a first subset of bit codings to supply data stored in a corresponding data register of said data register file to a corresponding functional unit, decode a double width instruction having a data operand field having one of said first subset of bit codings to supply data stored in a corresponding pair of data registers of said data register file to a corresponding functional unit operable upon double width data, decode a single width instruction having a data operand field having a predetermined first stream read operand coding from a second subset of bit codings separate from said first subset of bit codings to supply said data stored in said first stream head register to said corresponding functional unit, decode a single width instruction having a data operand field having a predetermined second stream read operand coding from said second subset of bit codings to supply said data stored in said second stream head register to said corresponding functional unit, and decode a double width instruction having a data operand field having a predetermined third stream read operand coding from said second subset of bit codings to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data. - View Dependent Claims (102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146)
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Specification