STREAM REFERENCE REGISTER WITH DOUBLE VECTOR AND DUAL SINGLE VECTOR OPERATING MODES

• US 20180011709A1
• Filed: 07/08/2016
• Published: 01/11/2018
• Est. Priority Date: 07/08/2016
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Zbiciak, Joseph
• Application Number:
  US15/205,246
• Publication Number:
  US 20180011709A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A streaming engine employed in a digital signal processor specifies a fixed read only data stream. Once fetched the data stream is stored in two head registers for presentation to functional units in the fixed order. Data use by the functional unit is preferably controlled using the input operand fields of the corresponding instruction. A first read only operand coding supplies data from the first head register. A first read/advance operand coding supplies data from the first head register and also advances the stream to the next sequential data elements. Corresponding second read only operand coding and second read/advance operand coding operate similarly with the second head register. A third read only operand coding supplies double width data from both head registers.

Claims

1. A digital signal processor comprising:

an instruction memory storing instructions each specifying a data processing operation and at least one data operand field;

an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand;

at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register;

a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including

a first stream head register storing a data element of said stream next to be used, and

a second stream head register storing a data element of said stream next to be used following said data stored in said first stream head register; and

wherein said instruction decoder is operable to

decode an instruction having a predetermined first stream read coding to supply said data stored in said first stream head register to said corresponding functional unit, and

decode an instruction having a predetermined second stream read coding to supply said data stored in said second stream head register to said corresponding functional unit.

2. The digital signal processor of claim 1, further comprising:

said instructions each include at least one data operand field specifying said at least one operand;

a data register file including a plurality of data registers designated by register number storing data;

said predetermined first stream read coding consists of said data operand field having a first stream read bit coding;

said predetermined second stream read coding consists of said data operand field having a second stream read bit coding;

wherein said instruction decoder is further operable to

decode an instruction having a data operand field having one of a first subset of bit codings to supply data stored in a corresponding data register of said data register file to a corresponding functional unit; and

decode an instruction having a data operand field having said predetermined first stream read bit coding to supply said data stored in said first stream head register to said corresponding functional unit, and

decode an instruction having a data operand field having said predetermined second stream read bit coding to supply said data stored in said second stream head register to said corresponding functional unit.

3. The digital signal processor of claim 1, wherein:

said instruction decoder is further operable to

decode an instruction having a predetermined first stream read/advance coding to supply said data stored in said first stream head register to said corresponding functional unit and advance said streaming engine by storing next sequential data elements of said stream in said first and second stream head registers, and

decode an instruction having a predetermined second stream read/advance coding to supply said data stored in said second stream head register to said corresponding functional unit and advance said streaming engine by storing next sequential data elements of said stream in said first and second stream head registers.

4. The digital signal processor of claim 3, further comprising:

said instructions each include at least one data operand field specifying said at least one operand;

a data register file including a plurality of data registers designated by register number storing data;

said predetermined first stream read/advance coding consists of said data operand field having a first stream read/advance bit coding;

said predetermined second stream read/advance coding consists of said data operand field having a second stream read/advance bit coding;

wherein said instruction decoder is further operable to

decode an instruction having a data operand field having one of a first subset bit codings to supply data stored in a corresponding data register of said data register file to a corresponding functional unit; and

decode an instruction having a data operand field having said predetermined first stream read/advance bit coding to supply said data stored in said first stream head register to said corresponding functional unit and to advance said streaming engine by storing a next sequential data element of said stream in said first and second stream head registers, and

decode an instruction having a data operand field having said predetermined second stream read/advance bit coding to supply said data stored in said second stream head register to said corresponding functional unit and to advance said streaming engine by storing a next sequential data element of said stream in said first and second stream head registers.

5. The digital signal processor of claim 1, wherein:

said at least one functional unit includes at least one functional unit operable upon double width data;

wherein said instruction decoder is further operable to

decode an instruction having a predetermined third stream read coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data.

6. The digital signal processor of claim 1, further comprising:

said instructions each include at least one data operand field specifying said at least one operand;

a data register file including a plurality of data registers designated by register number storing data;

said predetermined third stream read coding consists of said data operand field having a third stream read bit coding;

wherein said instruction decoder is further operable to

decode an instruction having a data operand field having a first subset bit codings to supply data stored in a corresponding data register of said data register file to a corresponding functional unit; and

decode an instruction having said predetermined third stream read bit coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data.

7. The digital signal processor of claim 1, wherein:

wherein said instruction decoder is further operable to

decode an instruction having a predetermined third stream read/advance coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data and advance said streaming engine by storing next sequential data elements of said stream in said first and second stream head registers.

8. The digital signal processor of claim 7, further comprising:

said instructions each include at least one data operand field specifying said at least one operand;

a data register file including a plurality of data registers designated by register number storing data;

said predetermined third stream read/advance coding consists of said data operand field having a third stream read/advance bit coding;

wherein said instruction decoder is further operable to

decode an instruction having a data operand field having a first subset bit codings to supply data stored in a corresponding data register of said data register file to a corresponding functional unit; and

decode an instruction having said predetermined third stream read/advance bit coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data and advance said streaming engine by storing next sequential data elements of said stream in said first and second stream head registers.

9. The digital signal processor of claim 1, wherein:

said instruction specified sequence of said plurality of data elements of a stream are specified by a start address and an element size.

10. The digital signal processor of claim 9, wherein:

said specified element size includes 8 bits of data.

11. The digital signal processor of claim 9, wherein:

said specified element size includes 16 bits of data.

12. The digital signal processor of claim 9, wherein:

said specified element size includes 32 bits of data.

13. The digital signal processor of claim 9, wherein:

said specified element size includes 64 bits of data.

14. The digital signal processor of claim 9, wherein:

said stream consists of an instruction specified number of data elements having said element size starting in memory at said start address.

15. The digital signal processor of claim 1, wherein:

each data element of said stream has a fixed data type.

16. The digital signal processor of claim 15, wherein:

said fixed data type of said data elements includes an unsigned integer.

17. The digital signal processor of claim 15, wherein:

said fixed data type of said data elements includes a signed integer.

18. The digital signal processor of claim 15, wherein:

said fixed data type of said data elements includes a floating point number.

19. The digital signal processor of claim 15, wherein:

said fixed data type of said data elements is a complex number having two equal sized sub-elements.

20. The digital signal processor of claim 19, wherein:

said two equally sized sub-elements comprise a first real sub-element and a second imaginary sub-element.

21. The digital signal processor of claim 19, wherein:

said two equally sized sub-elements comprise a first magnitude sub-element and a second angle sub-element.

22. The digital signal processor of claim 19, wherein:

each of said two equal sized sub-elements of data includes 8 bits.

23. The digital signal processor of claim 19, wherein:

each of said two equal sized sub-elements of data includes 16 bits.

24. The digital signal processor of claim 19, wherein:

each of said two equal sized sub-elements of data includes 32 bits.

25. The digital signal processor of claim 19, wherein:

each of said two equal sized sub-elements of data includes 64 bits.

26. The digital signal processor of claim 19, wherein:

said stream head register is divided into lanes;

said stream specifies no swap or swap for said complex number data type;

said stream engine

upon specification of no swap for a complex number data type, storing said two sub-elements of a complex number fetched data element in a lane of said stream head register in an order of storing said sub-elements in the memory, and

upon specification of swap for a complex number data type, storing said two sub-elements of a complex number fetched data element in a lane of said stream head register in an opposite order of storing said sub-elements in the memory.

27. The digital signal processor of claim 1, wherein:

said instruction specified sequence of said plurality of data elements of a stream are specified by data size of said data elements and an iteration number of a fetches of an inner loop.

28. The digital signal processor of claim 27, wherein:

said instruction specified plurality of data elements of a stream are specified at least in part by a stream definition template stored in a stream definition template register, said stream definition template register having an inner loop count data field specifying a number of iterations of said inner loop;

said stream engine includes an address generator generating a memory address of a next data element in said stream for fetching said next element from memory, said memory address generated by said address generator starting at said start address for a first data element of said stream and changing memory address by an amount equal to a specified data element size for following data elements until reaching said specified number of iterations of said inner loop.

29. The digital signal processor of claim 28, wherein:

said stream definition template register having a direction data field specifying a forward direction or a reverse direction;

said address generator for subsequent data elements changing said memory address to increasing memory addresses if said direction data field specifies a forward direction and changing said memory address to decreasing memory addresses if said direction data field specifies a reverse direction.

30. The digital signal processor of claim 28, wherein:

said stream definition template register having a loop dimension data field specifying a loop dimension and a loop count data field specifying a loop count for at least one outer loop;

said address generator upon completion of generation of data element addresses for a loop changing said memory address by an amount corresponding said loop dimension specified by said loop dimension data field of a next higher loop.

31. The digital signal processor of claim 28, wherein:

said address generator treats each loop dimension data field as a signed integer.

32. The digital signal processor of claim 28, wherein:

said stream definition template register having a transpose data field specifying a transpose mode or no transpose mode;

if said transpose data field specifies a transpose mode, said address generator transposing said inner loop and a first outer loop by following recall of a first data element at said start address

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop,

repeating a number of times equal to said loop count of said inner loop

changing said memory address by an amount corresponding to said data element size, and

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop.

33. The digital signal processor of claim 28, wherein:

said stream definition template register having a transpose data field specifying a transpose mode or no transpose mode, said transpose data field specifying a transpose granularity mode upon specifying said transpose mode;

if said transpose data field specifies a transpose mode, said address generator transposing said inner loop and a first outer loop by following recall of a first data element at said start address

repeating a number of times equal to a factor said loop dimension of said first outer loop exceeds said granularity,

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times corresponding to said granularity,

repeating a number of times equal to said loop count of said inner loop

changing said memory address by an amount corresponding to said data element size, and

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop.

34. The digital signal processor of claim 1, wherein:

said stream engine prefetches said data elements an instruction specified amount ahead of use by said at least one operational unit.

35. The digital signal processor of claim 1, wherein:

said stream head register is divided into lanes of said element data size; and

said streaming engine stores one data element of said stream in each lane of said stream head register.

36. The digital signal processor of claim 35, wherein:

if there are fewer remaining data elements than lanes, said streaming engine stores all 0'"'"'s in excess lanes.

37. The digital signal processor of claim 35, wherein:

said stream engine includes

an address generator generating a memory address of a next data element in said stream for fetching said next element from memory,

a data first-in-first-out buffer temporarily storing data elements fetched from memory, and

a formatter connected to said data first-in-first-out buffer and to said stream head register for recalling data elements from said data first-in-first-out buffer, performing instruction specified formatting upon each data element and storing formatted data elements in said stream head register.

38. The digital signal processor of claim 37, wherein:

said data first-in-first-out buffer discards stored data elements following supply to said at least one operational unit.

39. The digital signal processor of claim 35, wherein:

said stream specifies promotion or no promotion;

said stream engine

upon specification of no promotion, stores one data element of said stream in each lane of said stream head register of said element size, and

upon specification of promotion, promotes the data size of each data element and stores one data element of said stream in each lane of said stream head register of twice an original element size.

40. The digital signal processor of claim 39, wherein:

said stream specifies a data type including an unsigned integer data type; and

said stream engine upon specification of promotion, promotes the data size of each unsigned integer data type data element by zero extension.

41. The digital signal processor of claim 39, wherein:

said stream specifies a data type including a signed integer data type; and

said stream engine upon specification of promotion, promotes the data size of each signed integer data type data element by sign extension.

42. The digital signal processor of claim 39, wherein:

said stream specifies a data type including a floating point number data type; and

said stream engine upon specification of promotion, promotes a floating point number having a data size of 16 bits from a short (16-bit) floating point number to a single precision (32-bit) floating point number.

43. The digital signal processor of claim 39, wherein:

said stream specifies a data type including a floating point number data type; and

said stream engine upon specification of promotion, promotes a floating point number having a data size of 32 bits from a single precision (32-bit) floating point number to a double precision (64-bit) floating point number.

44. The digital signal processor of claim 1, further comprising:

a data coherence unit connected to said stream engine and to the memory, said data coherence unit operable to assure said stream is coherent with all writes to memory before said stream start instruction.

45. The digital signal processor of claim 44, further comprising:

said data coherence unit operable does not assure said stream is coherent with all writes to memory after said stream start instruction.

46. The digital signal processor of claim 45, further comprising:

said stream engine is responsive to a stream end instruction to stop recall of data; and

said instruction memory includes instructions controlling said at least one operational unit to avoid memory writes to memory addresses within a block of memory including said instruction specified plurality of data elements of said stream during an interval between a corresponding stream start instruction and a corresponding stream end instruction.

47. The digital signal processor of claim 1, further comprising:

a first parity bit generator receiving said stream, said first parity bit generator periodically forming first parity bits from said stream;

said stream engine is connected to said first parity generator to receive and store said stream and corresponding parity bits;

a second parity bit generator receiving said stored stream and corresponding parity bits at an output of said stream engine before supply to said at least one operational unit, said second parity bit generator operable to

periodically form second parity bits from said stream at said output of said stream engine,

compare said first parity bits with corresponding second parity bits, and

signal a parity fault if said first parity bits do not match said corresponding second parity bits.

48. The digital signal processor of claim 47, wherein:

said stream engine restarts fetching said stream upon a parity fault.

49. The digital signal processor of claim 1, wherein:

said instruction memory storing at least one stream save instruction and at least one stream restore instruction;

said stream engine in response to a stream save instruction saves state metadata of a current open stream and stops said current open stream; and

said stream engine in response to a stream restore instruction recalls previously saved state metadata of said current open stream, reopens said current open stream and resumes said current open stream corresponding to said stored metadata.

50. The digital signal processor of claim 1, further comprising:

a level one data cache connected to said at least one operational unit temporarily storing data for manipulation by said at least one operational unit, said level one data cache servicing said at least one operational unit memory reads and writes if corresponding data is stored therein (cache hit), otherwise (cache miss) referring said at least one operational unit memory reads and writes to a higher level memory; and

a level two cache connected to said level one data cache and to said stream engine, said level two cache temporarily storing data for manipulation by said at least one operational unit, said level two cache servicing level one data cache misses on memory reads and writes and stream engine memory reads if corresponding data is stored therein (cache hit), otherwise (cache miss) referring said at least one operational unit memory reads and writes and stream engine reads to a higher level memory.

51. The digital signal processor of claim 50, further comprising:

said level one data cache may temporarily store data not stored in said level two cache; and

a level two cache further upon a stream engine memory read if corresponding data is not stored therein (cache miss)

snooping said level one data cache to determine if said corresponding data is stored in said level one data cache,

if said corresponding data is stored in said level one data cache supplying said corresponding data from said level one data cache.

52. The digital signal processor of claim 1, wherein:

said at least one data operand field of said instructions consists of a first data operand field and a second data operand field;

said at least one functional unit includes a first operand input and a second operand input; and

wherein said instruction decoder is further operable to

decode an instruction having a first data operand field having a first predetermined read bit coding to supply said data stored in said first stream head register to said first operand input of said corresponding functional unit,

decode an instruction having a first data operand field having a second predetermined read bit coding to supply said data stored in said second stream head register to said first operand input of said corresponding functional unit,

decode an instruction having a second data operand field having said first predetermined read bit coding to supply said data stored in said first stream head register to said second operand input of said corresponding functional unit, and

decode an instruction having a second data operand field having said second predetermined read bit coding to supply said data stored in said second stream head register to said second operand input of said corresponding functional unit.

53. A digital signal processor comprising:

an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, said at least one instruction including a double width instruction;

an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand;

at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register, said at least one functional unit including at least one functional unit operable upon double width data in response to a double width instruction;

a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including

a first stream head register storing a data element of said stream next to be used, and

a second stream head register storing a data element of said stream next to be used following said data stored in said first stream head register; and

wherein said instruction decoder is operable to

decode an instruction having a predetermined double width stream read coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data.

54. The digital signal processor of claim 53, further comprising:

said instructions each include at least one data operand field specifying said at least one operand;

a data register file including a plurality of data registers designated by register number storing data;

said predetermined double width stream read coding consists of said data operand field having a predetermined double width stream read bit coding;

wherein said instruction decoder is further operable to

decode a double width instruction having a data operand field having a first subset bit codings to supply data stored in a corresponding pair of data registers of said data register file to a corresponding functional unit operable upon double width data; and

decode an instruction having said predetermined double width stream read bit coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data.

55. The digital signal processor of claim 54, wherein:

wherein said instruction decoder is further operable to

decode an instruction having a predetermined double width stream read/advance coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data and advance said streaming engine by storing next sequential data elements of said stream in said first and second stream head registers.

56. The digital signal processor of claim 55, further comprising:

said instructions each include at least one data operand field specifying said at least one operand;

a data register file including a plurality of data registers designated by register number storing data;

said predetermined double width stream read/advance coding consists of said data operand field having a double width stream read/advance bit coding;

wherein said instruction decoder is further operable to

decode an instruction having a data operand field having a first subset bit codings to supply data stored in a corresponding pair of data registers of said data register file to a corresponding functional unit operable upon double width data; and

decode an instruction having said predetermined double width stream read/advance bit coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data and advance said streaming engine by storing next sequential data elements of said stream in said first and second stream head registers.

57. The digital signal processor of claim 53, wherein:

said instruction specified sequence of said plurality of data elements of a stream are specified by a start address and an element size.

58. The digital signal processor of claim 57, wherein:

said specified element size includes 8 bits of data.

59. The digital signal processor of claim 57, wherein:

said specified element size includes 16 bits of data.

60. The digital signal processor of claim 57, wherein:

said specified element size includes 32 bits of data.

61. The digital signal processor of claim 57, wherein:

said specified element size includes 64 bits of data.

62. The digital signal processor of claim 57, wherein:

said stream consists of an instruction specified number of data elements having said element size starting in memory at said start address.

63. The digital signal processor of claim 53, wherein:

each data element of said stream has a fixed data type.

64. The digital signal processor of claim 63, wherein:

said fixed data type of said data elements includes an unsigned integer.

65. The digital signal processor of claim 63, wherein:

said fixed data type of said data elements includes a signed integer.

66. The digital signal processor of claim 63, wherein:

said fixed data type of said data elements includes a floating point number.

67. The digital signal processor of claim 63, wherein:

said fixed data type of said data elements is a complex number having two equal sized sub-elements.

68. The digital signal processor of claim 67, wherein:

said two equally sized sub-elements comprise a first real sub-element and a second imaginary sub-element.

69. The digital signal processor of claim 67, wherein:

said two equally sized sub-elements comprise a first magnitude sub-element and a second angle sub-element.

70. The digital signal processor of claim 67, wherein:

each of said two equal sized sub-elements of data includes 8 bits.

71. The digital signal processor of claim 67, wherein:

each of said two equal sized sub-elements of data includes 16 bits.

72. The digital signal processor of claim 67, wherein:

each of said two equal sized sub-elements of data includes 32 bits.

73. The digital signal processor of claim 67, wherein:

each of said two equal sized sub-elements of data includes 64 bits.

74. The digital signal processor of claim 67, wherein:

said stream head register is divided into lanes;

said stream specifies no swap or swap for said complex number data type;

said stream engine

upon specification of no swap for a complex number data type, storing said two sub-elements of a complex number fetched data element in a lane of said stream head register in an order of storing said sub-elements in the memory, and

upon specification of swap for a complex number data type, storing said two sub-elements of a complex number fetched data element in a lane of said stream head register in an opposite order of storing said sub-elements in the memory.

75. The digital signal processor of claim 53, wherein:

said instruction specified sequence of said plurality of data elements of a stream are specified by data size of said data elements and an iteration number of a fetches of an inner loop.

76. The digital signal processor of claim 75, wherein:

said instruction specified plurality of data elements of a stream are specified at least in part by a stream definition template stored in a stream definition template register, said stream definition template register having an inner loop count data field specifying a number of iterations of said inner loop;

said stream engine includes an address generator generating a memory address of a next data element in said stream for fetching said next element from memory, said memory address generated by said address generator starting at said start address for a first data element of said stream and changing memory address by an amount equal to a specified data element size for following data elements until reaching said specified number of iterations of said inner loop.

77. The digital signal processor of claim 76, wherein:

said stream definition template register having a direction data field specifying a forward direction or a reverse direction;

said address generator for subsequent data elements changing said memory address to increasing memory addresses if said direction data field specifies a forward direction and changing said memory address to decreasing memory addresses if said direction data field specifies a reverse direction.

78. The digital signal processor of claim 76, wherein:

said stream definition template register having a loop dimension data field specifying a loop dimension and a loop count data field specifying a loop count for at least one outer loop;

said address generator upon completion of generation of data element addresses for a loop changing said memory address by an amount corresponding said loop dimension specified by said loop dimension data field of a next higher loop.

79. The digital signal processor of claim 76, wherein:

said address generator treats each loop dimension data field as a signed integer.

80. The digital signal processor of claim 76, wherein:

said stream definition template register having a transpose data field specifying a transpose mode or no transpose mode;

if said transpose data field specifies a transpose mode, said address generator transposing said inner loop and a first outer loop by following recall of a first data element at said start address

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop,

repeating a number of times equal to said loop count of said inner loop

changing said memory address by an amount corresponding to said data element size, and

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop.

81. The digital signal processor of claim 76, wherein:

said stream definition template register having a transpose data field specifying a transpose mode or no transpose mode, said transpose data field specifying a transpose granularity mode upon specifying said transpose mode;

if said transpose data field specifies a transpose mode, said address generator transposing said inner loop and a first outer loop by following recall of a first data element at said start address

repeating a number of times equal to a factor said loop dimension of said first outer loop exceeds said granularity,

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times corresponding to said granularity,

repeating a number of times equal to said loop count of said inner loop

changing said memory address by an amount corresponding to said data element size, and

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop.

82. The digital signal processor of claim 53, wherein:

said stream engine prefetches said data elements an instruction specified amount ahead of use by said at least one operational unit.

83. The digital signal processor of claim 53, wherein:

said stream head register is divided into lanes of said element data size; and

said streaming engine stores one data element of said stream in each lane of said stream head register.

84. The digital signal processor of claim 83, wherein:

if there are fewer remaining data elements than lanes, said streaming engine stores all 0'"'"'s in excess lanes.

85. The digital signal processor of claim 83, wherein:

said stream engine includes

an address generator generating a memory address of a next data element in said stream for fetching said next element from memory,

a data first-in-first-out buffer temporarily storing data elements fetched from memory, and

a formatter connected to said data first-in-first-out buffer and to said stream head register for recalling data elements from said data first-in-first-out buffer, performing instruction specified formatting upon each data element and storing formatted data elements in said stream head register.

86. The digital signal processor of claim 83, wherein:

said data first-in-first-out buffer discards stored data elements following supply to said at least one operational unit.

87. The digital signal processor of claim 83, wherein:

said stream specifies promotion or no promotion;

said stream engine

upon specification of no promotion, stores one data element of said stream in each lane of said stream head register of said element size, and

upon specification of promotion, promotes the data size of each data element and stores one data element of said stream in each lane of said stream head register of twice an original element size.

88. The digital signal processor of claim 87, wherein:

said stream specifies a data type including an unsigned integer data type; and

said stream engine upon specification of promotion, promotes the data size of each unsigned integer data type data element by zero extension.

89. The digital signal processor of claim 87, wherein:

said stream specifies a data type including a signed integer data type; and

said stream engine upon specification of promotion, promotes the data size of each signed integer data type data element by sign extension.

90. The digital signal processor of claim 87, wherein:

said stream specifies a data type including a floating point number data type; and

said stream engine upon specification of promotion, promotes a floating point number having a data size of 16 bits from a short (16-bit) floating point number to a single precision (32-bit) floating point number.

91. The digital signal processor of claim 87, wherein:

said stream specifies a data type including a floating point number data type; and

said stream engine upon specification of promotion, promotes a floating point number having a data size of 32 bits from a single precision (32-bit) floating point number to a double precision (64-bit) floating point number.

92. The digital signal processor of claim 53, further comprising:

a data coherence unit connected to said stream engine and to the memory, said data coherence unit operable to assure said stream is coherent with all writes to memory before said stream start instruction.

93. The digital signal processor of claim 92, further comprising:

said data coherence unit operable does not assure said stream is coherent with all writes to memory after said stream start instruction.

94. The digital signal processor of claim 93, further comprising:

said stream engine is responsive to a stream end instruction to stop recall of data; and

said instruction memory includes instructions controlling said at least one operational unit to avoid memory writes to memory addresses within a block of memory including said instruction specified plurality of data elements of said stream during an interval between a corresponding stream start instruction and a corresponding stream end instruction.

95. The digital signal processor of claim 53, further comprising:

a first parity bit generator receiving said stream, said first parity bit generator periodically forming first parity bits from said stream;

said stream engine is connected to said first parity generator to receive and store said stream and corresponding parity bits;

a second parity bit generator receiving said stored stream and corresponding parity bits at an output of said stream engine before supply to said at least one operational unit, said second parity bit generator operable to

periodically form second parity bits from said stream at said output of said stream engine,

compare said first parity bits with corresponding second parity bits, and

signal a parity fault if said first parity bits do not match said corresponding second parity bits.

96. The digital signal processor of claim 95, wherein:

said stream engine restarts fetching said stream upon a parity fault.

97. The digital signal processor of claim 53, wherein:

said instruction memory storing at least one stream save instruction and at least one stream restore instruction;

said stream engine in response to a stream save instruction saves state metadata of a current open stream and stops said current open stream; and

said stream engine in response to a stream restore instruction recalls previously saved state metadata of said current open stream, reopens said current open stream and resumes said current open stream corresponding to said stored metadata.

98. The digital signal processor of claim 53, further comprising:

a level one data cache connected to said at least one operational unit temporarily storing data for manipulation by said at least one operational unit, said level one data cache servicing said at least one operational unit memory reads and writes if corresponding data is stored therein (cache hit), otherwise (cache miss) referring said at least one operational unit memory reads and writes to a higher level memory; and

a level two cache connected to said level one data cache and to said stream engine, said level two cache temporarily storing data for manipulation by said at least one operational unit, said level two cache servicing level one data cache misses on memory reads and writes and stream engine memory reads if corresponding data is stored therein (cache hit), otherwise (cache miss) referring said at least one operational unit memory reads and writes and stream engine reads to a higher level memory.

99. The digital signal processor of claim 98, further comprising:

said level one data cache may temporarily store data not stored in said level two cache; and

a level two cache further upon a stream engine memory read if corresponding data is not stored therein (cache miss)

snooping said level one data cache to determine if said corresponding data is stored in said level one data cache,

if said corresponding data is stored in said level one data cache supplying said corresponding data from said level one data cache.

100. The digital signal processor of claim 53, wherein:

said at least one data operand field of said instructions consists of a first data operand field and a second data operand field;

said at least one functional unit includes a first operand input and a second operand input; and

wherein said instruction decoder is further operable to

decode an instruction having a first data operand field having a first predetermined read bit coding to supply said data stored in said first stream head register to said first operand input of said corresponding functional unit,

decode an instruction having a first data operand field having a second predetermined read bit coding to supply said data stored in said second stream head register to said first operand input of said corresponding functional unit,

decode an instruction having a second data operand field having said first predetermined read bit coding to supply said data stored in said first stream head register to said second operand input of said corresponding functional unit, and

decode an instruction having a second data operand field having said second predetermined read bit coding to supply said data stored in said second stream head register to said second operand input of said corresponding functional unit.

101. A digital signal processor comprising:

an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, said instructions including at least one single width instruction and at least one double width instruction, said instructions each including at least one data operand field specifying at least one operand;

an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand;

at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register, said at least one functional unit including at least one functional unit operable upon double width data in response to a double width instruction;

a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including

a first stream head register storing a data element of said stream next to be used, and

a second stream head register storing a data element of said stream next to be used following said data stored in said first stream head register; and

wherein said instruction decoder is operable to

decode a single width instruction having a data operand field having one of a first subset of bit codings to supply data stored in a corresponding data register of said data register file to a corresponding functional unit,

decode a double width instruction having a data operand field having one of said first subset of bit codings to supply data stored in a corresponding pair of data registers of said data register file to a corresponding functional unit operable upon double width data,

decode a single width instruction having a data operand field having a predetermined first stream read operand coding from a second subset of bit codings separate from said first subset of bit codings to supply said data stored in said first stream head register to said corresponding functional unit,

decode a single width instruction having a data operand field having a predetermined second stream read operand coding from said second subset of bit codings to supply said data stored in said second stream head register to said corresponding functional unit, and

decode a double width instruction having a data operand field having a predetermined third stream read operand coding from said second subset of bit codings to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data.

102. The digital signal processor of claim 101, wherein:

said instruction decoder is further operable to

decode a single width instruction having a data operand field having a predetermined first stream read/advance operand coding from said second subset of bit coding to supply said data stored in said first stream head register to said corresponding functional unit and advance said streaming engine by storing next sequential data elements of said stream in said first and second stream head registers,

decode a single width instruction having a data operand field having a predetermined second stream read/advance operand coding from said second subset of bit coding to supply said data stored in said second stream head register to said corresponding functional unit and advance said streaming engine by storing next sequential data elements of said stream in said first and second stream head registers, and

decode an instruction having a data operand field having a predetermined third stream read coding from said second subset of bit coding to supply said data stored in both said first stream head register and said second stream head register to said functional unit operable upon double width data.

103. The digital signal processor of claim 102, wherein:

said instruction specified sequence of said plurality of data elements of a stream are specified by a start address and an element size.

104. The digital signal processor of claim 103, wherein:

said specified element size includes 8 bits of data.

105. The digital signal processor of claim 103, wherein:

said specified element size includes 16 bits of data.

106. The digital signal processor of claim 103, wherein:

said specified element size includes 32 bits of data.

107. The digital signal processor of claim 103, wherein:

said specified element size includes 64 bits of data.

108. The digital signal processor of claim 103, wherein:

said stream consists of an instruction specified number of data elements having said element size starting in memory at said start address.

109. The digital signal processor of claim 101, wherein:

each data element of said stream has a fixed data type.

110. The digital signal processor of claim 109, wherein:

said fixed data type of said data elements includes an unsigned integer.

111. The digital signal processor of claim 109, wherein:

said fixed data type of said data elements includes a signed integer.

112. The digital signal processor of claim 109, wherein:

said fixed data type of said data elements includes a floating point number.

113. The digital signal processor of claim 109, wherein:

said fixed data type of said data elements is a complex number having two equal sized sub-elements.

114. The digital signal processor of claim 113, wherein:

said two equally sized sub-elements comprise a first real sub-element and a second imaginary sub-element.

115. The digital signal processor of claim 113, wherein:

said two equally sized sub-elements comprise a first magnitude sub-element and a second angle sub-element.

116. The digital signal processor of claim 113, wherein:

each of said two equal sized sub-elements of data includes 8 bits.

117. The digital signal processor of claim 113, wherein:

each of said two equal sized sub-elements of data includes 16 bits.

118. The digital signal processor of claim 113, wherein:

each of said two equal sized sub-elements of data includes 32 bits.

119. The digital signal processor of claim 113, wherein:

each of said two equal sized sub-elements of data includes 64 bits.

120. The digital signal processor of claim 113, wherein:

said stream head register is divided into lanes;

said stream specifies no swap or swap for said complex number data type;

said stream engine

upon specification of no swap for a complex number data type, storing said two sub-elements of a complex number fetched data element in a lane of said stream head register in an order of storing said sub-elements in the memory, and

upon specification of swap for a complex number data type, storing said two sub-elements of a complex number fetched data element in a lane of said stream head register in an opposite order of storing said sub-elements in the memory.

121. The digital signal processor of claim 101, wherein:

said instruction specified sequence of said plurality of data elements of a stream are specified by data size of said data elements and an iteration number of a fetches of an inner loop.

122. The digital signal processor of claim 121, wherein:

said instruction specified plurality of data elements of a stream are specified at least in part by a stream definition template stored in a stream definition template register, said stream definition template register having an inner loop count data field specifying a number of iterations of said inner loop;

said stream engine includes an address generator generating a memory address of a next data element in said stream for fetching said next element from memory, said memory address generated by said address generator starting at said start address for a first data element of said stream and changing memory address by an amount equal to a specified data element size for following data elements until reaching said specified number of iterations of said inner loop.

123. The digital signal processor of claim 122, wherein:

said stream definition template register having a direction data field specifying a forward direction or a reverse direction;

said address generator for subsequent data elements changing said memory address to increasing memory addresses if said direction data field specifies a forward direction and changing said memory address to decreasing memory addresses if said direction data field specifies a reverse direction.

124. The digital signal processor of claim 122, wherein:

said stream definition template register having a loop dimension data field specifying a loop dimension and a loop count data field specifying a loop count for at least one outer loop;

said address generator upon completion of generation of data element addresses for a loop changing said memory address by an amount corresponding said loop dimension specified by said loop dimension data field of a next higher loop.

125. The digital signal processor of claim 122, wherein:

said address generator treats each loop dimension data field as a signed integer.

126. The digital signal processor of claim 122, wherein:

said stream definition template register having a transpose data field specifying a transpose mode or no transpose mode;

if said transpose data field specifies a transpose mode, said address generator transposing said inner loop and a first outer loop by following recall of a first data element at said start address

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop,

repeating a number of times equal to said loop count of said inner loop

changing said memory address by an amount corresponding to said data element size, and

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop.

127. The digital signal processor of claim 122, wherein:

said stream definition template register having a transpose data field specifying a transpose mode or no transpose mode, said transpose data field specifying a transpose granularity mode upon specifying said transpose mode;

if said transpose data field specifies a transpose mode, said address generator transposing said inner loop and a first outer loop by following recall of a first data element at said start address

repeating a number of times equal to a factor said loop dimension of said first outer loop exceeds said granularity,

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times corresponding to said granularity,

repeating a number of times equal to said loop count of said inner loop

changing said memory address by an amount corresponding to said data element size, and

changing said memory address by an amount corresponding to said loop dimension of said first outer loop and recalling a next data element at said memory address a number of times equal to said loop count of said first outer loop.

128. The digital signal processor of claim 101, wherein:

said stream engine prefetches said data elements an instruction specified amount ahead of use by said at least one operational unit.

129. The digital signal processor of claim 101, wherein:

said stream head register is divided into lanes of said element data size; and

said streaming engine stores one data element of said stream in each lane of said stream head register.

130. The digital signal processor of claim 129, wherein:

if there are fewer remaining data elements than lanes, said streaming engine stores all 0'"'"'s in excess lanes.

131. The digital signal processor of claim 129, wherein:

said stream engine includes

an address generator generating a memory address of a next data element in said stream for fetching said next element from memory,

a data first-in-first-out buffer temporarily storing data elements fetched from memory, and

a formatter connected to said data first-in-first-out buffer and to said stream head register for recalling data elements from said data first-in-first-out buffer, performing instruction specified formatting upon each data element and storing formatted data elements in said stream head register.

132. The digital signal processor of claim 131, wherein:

said data first-in-first-out buffer discards stored data elements following supply to said at least one operational unit.

133. The digital signal processor of claim 129, wherein:

said stream specifies promotion or no promotion;

said stream engine

upon specification of no promotion, stores one data element of said stream in each lane of said stream head register of said element size, and

upon specification of promotion, promotes the data size of each data element and stores one data element of said stream in each lane of said stream head register of twice an original element size.

134. The digital signal processor of claim 132, wherein:

said stream specifies a data type including an unsigned integer data type; and

said stream engine upon specification of promotion, promotes the data size of each unsigned integer data type data element by zero extension.

135. The digital signal processor of claim 132, wherein:

said stream specifies a data type including a signed integer data type; and

said stream engine upon specification of promotion, promotes the data size of each signed integer data type data element by sign extension.

136. The digital signal processor of claim 132, wherein:

said stream specifies a data type including a floating point number data type; and

said stream engine upon specification of promotion, promotes a floating point number having a data size of 16 bits from a short (16-bit) floating point number to a single precision (32-bit) floating point number.

137. The digital signal processor of claim 132, wherein:

said stream specifies a data type including a floating point number data type; and

said stream engine upon specification of promotion, promotes a floating point number having a data size of 32 bits from a single precision (32-bit) floating point number to a double precision (64-bit) floating point number.

138. The digital signal processor of claim 101, further comprising:

a data coherence unit connected to said stream engine and to the memory, said data coherence unit operable to assure said stream is coherent with all writes to memory before said stream start instruction.

139. The digital signal processor of claim 138, further comprising:

said data coherence unit operable does not assure said stream is coherent with all writes to memory after said stream start instruction.

140. The digital signal processor of claim 139, further comprising:

said stream engine is responsive to a stream end instruction to stop recall of data; and

said instruction memory includes instructions controlling said at least one operational unit to avoid memory writes to memory addresses within a block of memory including said instruction specified plurality of data elements of said stream during an interval between a corresponding stream start instruction and a corresponding stream end instruction.

141. The digital signal processor of claim 101, further comprising:

a first parity bit generator receiving said stream, said first parity bit generator periodically forming first parity bits from said stream;

said stream engine is connected to said first parity generator to receive and store said stream and corresponding parity bits;

a second parity bit generator receiving said stored stream and corresponding parity bits at an output of said stream engine before supply to said at least one operational unit, said second parity bit generator operable to

periodically form second parity bits from said stream at said output of said stream engine,

compare said first parity bits with corresponding second parity bits, and

signal a parity fault if said first parity bits do not match said corresponding second parity bits.

142. The digital signal processor of claim 141, wherein:

said stream engine restarts fetching said stream upon a parity fault.

143. The digital signal processor of claim 101, wherein:

said instruction memory storing at least one stream save instruction and at least one stream restore instruction;

said stream engine in response to a stream save instruction saves state metadata of a current open stream and stops said current open stream; and

said stream engine in response to a stream restore instruction recalls previously saved state metadata of said current open stream, reopens said current open stream and resumes said current open stream corresponding to said stored metadata.

144. The digital signal processor of claim 101, further comprising:

a level one data cache connected to said at least one operational unit temporarily storing data for manipulation by said at least one operational unit, said level one data cache servicing said at least one operational unit memory reads and writes if corresponding data is stored therein (cache hit), otherwise (cache miss) referring said at least one operational unit memory reads and writes to a higher level memory; and

a level two cache connected to said level one data cache and to said stream engine, said level two cache temporarily storing data for manipulation by said at least one operational unit, said level two cache servicing level one data cache misses on memory reads and writes and stream engine memory reads if corresponding data is stored therein (cache hit), otherwise (cache miss) referring said at least one operational unit memory reads and writes and stream engine reads to a higher level memory.

145. The digital signal processor of claim 144, further comprising:

said level one data cache may temporarily store data not stored in said level two cache; and

a level two cache further upon a stream engine memory read if corresponding data is not stored therein (cache miss)

snooping said level one data cache to determine if said corresponding data is stored in said level one data cache,

if said corresponding data is stored in said level one data cache supplying said corresponding data from said level one data cache.

146. The digital signal processor of claim 101, wherein:

said at least one data operand field of said instructions consists of a first data operand field and a second data operand field;

said at least one functional unit includes a first operand input and a second operand input; and

wherein said instruction decoder is further operable to

decode an instruction having a first data operand field having a first predetermined read bit coding to supply said data stored in said first stream head register to said first operand input of said corresponding functional unit,

decode an instruction having a first data operand field having a second predetermined read bit coding to supply said data stored in said second stream head register to said first operand input of said corresponding functional unit,

decode an instruction having a second data operand field having said first predetermined read bit coding to supply said data stored in said first stream head register to said second operand input of said corresponding functional unit, and

decode an instruction having a second data operand field having said second predetermined read bit coding to supply said data stored in said second stream head register to said second operand input of said corresponding functional unit.