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STREAM REFERENCE REGISTER WITH DOUBLE VECTOR AND DUAL SINGLE VECTOR OPERATING MODES

  • US 20180011709A1
  • Filed: 07/08/2016
  • Published: 01/11/2018
  • Est. Priority Date: 07/08/2016
  • Status: Abandoned Application
First Claim
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1. A digital signal processor comprising:

  • an instruction memory storing instructions each specifying a data processing operation and at least one data operand field;

    an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand;

    at least one functional unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register;

    a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine includinga first stream head register storing a data element of said stream next to be used, anda second stream head register storing a data element of said stream next to be used following said data stored in said first stream head register; and

    wherein said instruction decoder is operable todecode an instruction having a predetermined first stream read coding to supply said data stored in said first stream head register to said corresponding functional unit, anddecode an instruction having a predetermined second stream read coding to supply said data stored in said second stream head register to said corresponding functional unit.

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