Word Line Dependent Pass Voltages In Non-Volatile Memory

• US 20180012667A1
• Filed: 07/07/2016
• Published: 01/11/2018
• Est. Priority Date: 07/07/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Costa, Xiying
• Granted Patent: US 10,049,758 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.

Claims

1. An apparatus, comprising:

a group of memory cells coupled to a select gate;

a program circuit configured to program a first memory cell of the group before programming a second memory cell of the group; and

a sense circuit configured to sense the first memory cell by applying a first pass voltage to two or more memory cells positioned between the select gate and the first memory cell, the sense circuit configured to sense the second memory cell by applying a second pass voltage to the two or more memory cells, the second pass voltage is different from the first pass voltage.

2. The apparatus of claim 1, wherein:

the second pass voltage is higher than the first pass voltage;

the sense circuit is configured to sense the first memory cell as part of a program verification operation by applying a verify voltage to the first memory cell and applying the first pass voltage to the two or more memory cells; and

the sense circuit is configured to sense the second memory cell as part of a program verification operation by applying the verify voltage to the second memory cell and applying the second pass voltage to the two or more memory cells.

3. The apparatus of claim 2, wherein:

the sense circuit verifies that the first memory cell is programmed by applying a third pass voltage to two memory cells adjacent to the first memory cell and applying the first pass voltage to the two or more memory cells;

the sense circuit verifies that the second memory cell is programmed by applying the third pass voltage to two memory cells adjacent to the second memory cell and applying the second pass voltage to the two or more memory cells; and

the third pass voltage is higher than the second pass voltage.

4. The apparatus of claim 3, wherein:

the select gate is a source select gate coupled between the group of memory cells and a source line;

the first memory cell is positioned between the second memory cell and the source select gate; and

the two or more memory cells receiving the first pass voltage are two or more memory cells that are subjected to programming after erase and prior to programming the first memory cell;

the sense circuit is configured to apply the first pass voltage to each other memory cell of the group that is positioned between the first memory cell and the source select gate and that has been subjected to programming after erase and prior to programming the first memory cell.

5. The apparatus of claim 4, wherein:

the sense circuit applies a third pass voltage to two or more unprogrammed memory cells positioned between the first memory cell and a drain select gate while applying the first pass voltage to the two or more previously programmed memory cells, the third pass voltage is less than the first pass voltage; and

the verification circuit applies the third pass voltage to the two or more unprogrammed memory cells while applying the second pass voltage to the two or more previously programmed memory cells.

6. The apparatus of claim 1, wherein:

the first pass voltage is higher than the second pass voltage;

the sense circuit is configured to sense the first memory cell as part of a read operation by applying a read reference voltage to the first memory cell and applying the first pass voltage to the two or more memory cells; and

the sense circuit is configured to sense the second memory cell as part of a read operation by applying the read reference voltage to the second memory cell and applying the second pass voltage to the two or more memory cells.

7. An apparatus, comprising:

a plurality of word lines coupled to a plurality of memory cells; and

a program verification circuit, the program verification circuit configured to apply a first pass voltage to a previously programmed word line to verify a first selected word line and configured to apply a second pass voltage to the previously programmed word line to verify a second selected word line, the second pass voltage is higher than the first pass voltage and the second selected word line is programmed subsequent to the first selected word line.

8. The apparatus of claim 7, further comprising:

a source select gate coupled to the plurality of memory cells; and

wherein the previously programmed word line is between the first selected word line and the source select gate; and

wherein the first selected word line is positioned between the second selected word line and the source select gate.

9. The apparatus of claim 8, wherein:

the previously programmed word line is a first previously programmed word line;

the program verification circuit applies the first pass voltage to a second previously programmed word line to verify the first selected word line; and

the program verification circuit applies the second pass voltage to the second previously programmed word line to verify the second selected word line.

10. The apparatus of claim 7, wherein:

the program verification circuit applies a third pass voltage to the previously programmed word line to verify a third selected word line of the plurality;

the third pass voltage is higher than the second pass voltage; and

the third selected word line is programmed subsequent to the second selected word line.

11. The apparatus of claim 7, wherein:

the previously programmed word line is a first previously programmed word line;

the program verification circuit verifies the first selected word line by applying a verify voltage to the first selected word line and applying the first pass voltage to a first set of previously programmed word lines including the first previously programmed word line; and

the program verification circuit verifies the second selected word line by applying the verify voltage to the second selected word line and applying the second pass voltage to a second set of previously programmed word lines, the second set of previously programmed word lines includes the first set of previously programmed word lines and one or more additional previously programmed word lines.

12. The apparatus of claim 7, wherein:

the program verification circuit applies a third pass voltage to an unprogrammed word line of the plurality to verify the first selected word line, the third pass voltage is lower than the first pass voltage; and

the program verification circuit applies a fourth pass voltage to the unprogrammed word line to verify the second selected word line, the fourth pass voltage is higher than the third pass voltage and lower than the first pass voltage.

13. The apparatus of claim 7, wherein:

the program verification circuit applies the first pass voltage to the previously programmed word line while applying a first verify voltage to the first selected word line;

the program verification circuit applies the second pass voltage to the previously programmed word line while applying the first verify voltage to the second selected word line;

the program verification circuit applies a third pass voltage to the previously programmed word line while applying a second verify voltage to the first selected word line, the second verify voltage is higher than the first verify voltage, the first pass voltage is higher than the third pass voltage; and

the program verification circuit applies a fourth pass voltage to the previously programmed word line while applying the second verify voltage to the second selected word line, the fourth pass voltage is higher than the third pass voltage and lower than the second pass voltage.

14. The apparatus of claim 7, wherein:

the plurality of non-volatile memory cells is part of a non-volatile memory array;

the non-volatile memory array is arranged in a three dimensional structure; and

the plurality of non-volatile memory cells is arranged as a NAND string.

15. A method, comprising:

applying a first pass voltage to two or more word lines positioned between a selected word line and a select gate during program verification if the selected word line is in a first zone of word lines; and

applying a second pass voltage to two or more word lines positioned between the selected word line and the select gate during program verification if the selected word line is in a second zone of word lines, the second pass voltage is higher than the first pass voltage, the first zone is positioned between the second zone and the select gate.

16. The method of claim 15, further comprising:

applying a third pass voltage to first and second adjacent word lines of the selected word line during program verification if the selected word line is in the first zone, the third pass voltage is higher than the second pass voltage; and

applying the third pass voltage to the first and second adjacent word lines during program verification if the selected word line is in the second zone.

17. The method of claim 16, further comprising:

applying a first verify voltage to the selected word line while applying the first pass voltage if the selected word line is in the first zone;

applying the first verify voltage to the selected word line while applying the second pass voltage if the selected word line is in the second zone;

applying a second verify voltage to the selected word line while applying a fourth pass voltage to the two or more word lines if the selected word line is in the first zone, the second verify voltage is higher than the first verify voltage, the first pass voltage is higher than the fourth pass voltage; and

applying the second verify voltage to the selected word line while applying a fifth pass voltage to the two or more word lines if the selected word line is in the second zone, the fifth pass voltage is higher than the fourth pass voltage and lower than the second pass voltage.

18. The method of claim 15, further comprising:

programming the two or more word lines; and

programming the selected word line after programming the two or more word lines;

wherein the two or more word lines are two are more word lines that are subjected to programming after erase and prior to programming the selected word line; and

wherein programming for the first zone of word lines begins prior to programming for the second zone of word lines.

19. An apparatus, comprising:

a source line;

a plurality of word lines;

means for applying to an unselected word line between the source line and a selected word line a first pass voltage based at least in part on applying a verify voltage to a first selected word line, wherein the first selected word line is in a first zone of word lines of the plurality;

means for applying to the unselected word line a second pass voltage based at least in part on applying the verify voltage to a second selected word line, wherein the second selected word line is in a second zone of word lines of the plurality, the second pass voltage is higher than the first pass voltage, the first zone is between the second zone and the source line and is programmed before the second zone; and

means for applying to the unselected word line a third pass voltage based at least in part on applying the verify voltage to a third selected word line, wherein the third selected word line is in a third zone of word lines of the plurality, the third pass voltage is higher than the second pass voltage, the second zone is between the third zone and the first zone and is programmed before the third zone.

20. The apparatus of claim 19, wherein the unselected word line is a first unselected word line, the apparatus further comprising:

a bit line;

means for applying to a second unselected word line between the bit line and the selected word line a fourth pass voltage based at least in part on applying the verify voltage if the selected word line is in the first zone, the fourth pass voltage is lower than the first pass voltage;

means for applying to the second unselected word line a fifth pass voltage based at least in part on applying the verify voltage if the selected word line is in the second zone, the fifth pass voltage is lower than the second pass voltage and higher than the fourth pass voltage; and

means for applying to the second unselected word line a sixth pass voltage based at least in part on applying the verify voltage if the selected word line is in the third zone, the sixth pass voltage is lower than the third pass voltage and higher than the fifth pass voltage.