METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR

• US 20180012766A1
• Filed: 06/20/2017
• Published: 01/11/2018
• Est. Priority Date: 06/20/2016
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Pollet, Olivier, Garcia-Barros, Maxime, Posseme, Nicolas
• Granted Patent: US 9,947,541 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x≦0.2, and having a pH less than or equal to 1.5.

Claims

1-16. -16. (canceled)

17. A method for forming spacers of a gate of a field effect transistor, the gate comprising sides and a top and being located above a layer made of a semiconductor material, the method comprising:

a step of forming a dielectric layer that covers the gate of the transistor;

after the step of forming the dielectric layer, at least one step of modifying said dielectric layer by ion implantation at least in portions of the dielectric layer that are located on a top of the gate and on either side of the gate and which are perpendicular to the sides of the gate by retaining non-modified portions of the dielectric layer coveting the sides of the gate, said non-modified portions being at least non-modified over their entire thickness the ions having a hydrogen base and/or a helium base; and

at least one step of removing the modified dielectric layer using a selective etching of the modified dielectric layer relative to the layer made of a semiconductor material and relative to the non-modified dielectric layer,

wherein the dielectric layer is made of a material chosen from among a silicon nitride, SiC, SiCN, and SiCBN, and

wherein the selective etching of the modified dielectric layer comprises a wet etching based on a solution comprising hydrofluoric acid diluted to x % by weight, with x≦

0.2, and having a pH less than or equal to 1.5.

18. The method according to claim 17, wherein the pH is less than or equal to 1.3.

19. The method according to claim 17, wherein x≦

0.15.

20. The method according to claim 17, wherein x is substantially equal to 0.1.

21. The method according to claim 17, wherein the solution is obtained by adding at least one material chosen from among hydrochloric acid, sulfuric acid, and nitric acid.

22. The method according to claim 17, wherein the dielectric layer is a layer of SiN.

23. The method according to claim 17, wherein the selective etching of the modified dielectric layer relative to the non-modified dielectric layer has a selectivity greater than or equal to 11.

24. The method according to claim 17, further comprising, before the step of removing, a step of forming a mask located at the top of the gate, the mask being made from a silicon oxide of SiO_y, with y being an integer greater than or equal to 1.

25. The method according to claim 17, further comprising, before the step of removing, a step of forming an insulation trench that extends through the layer of the semiconductor material, the insulation trench being made from a silicon oxide of SiO_y, with y being an integer greater than or equal to 1.

26. The method according to claim 24, wherein the selective etching of the modified dielectric layer relative to the silicon oxide of SiO_y has a selectivity greater than or equal to 33.

27. The method according to claim 17, further comprising a single step of modification so as to modify the dielectric layer throughout its entire thickness over all of surfaces parallel to a plane of a substrate whereon the gate is disposed and so as to not modify the dielectric layer throughout its entire thickness on surfaces perpendicular to the plane.

28. The method according to claim 17, wherein the step of modifying the dielectric layer by ion implantation comprises exposing the dielectric layer to a plasma and creating an anisotropic ion implantation according to a predetermined direction parallel to the sides of the gate.

29. The method according to claim 28, wherein ions in the plasma have a hydrogen base and/or a helium base.

30. The method according to claim 28, wherein the plasma is obtained by injection into a reactor of gas chosen from among helium, hydrogen, and ammonia, where a corresponding injection flow rate being from 50 sccm to 500 sccm if the gas is helium, being from 10 sccm to 500 sccm if the gas is hydrogen, and being from 10 sccm to 500 sccm if the gas is ammonia.

31. The method according to claim 17, wherein the step of modifying the dielectric layer is performed with a polarization power or a source power ranging from 20V to 500V, with a pressure ranging from 5 mTorr to 100 mTorr, at a temperature ranging from 10°

C. to 100°

C., and for a duration of a few seconds to several hundred seconds.

32. The method according to claim 17, wherein the transistor is a FDSOI transistor or a FinFET transistor.