System and Method for the Fluidic Assembly of Micro-LEDs Utilizing Negative Pressure

• US 20180012873A1
• Filed: 08/31/2017
• Published: 01/11/2018
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Elux Inc.
• Original Assignee: Elux Inc.
• Inventors: Lee, Jong-Jan, Schuele, Paul J.
• Granted Patent: US 10,535,640 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/133603 with LEDs
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32055 being circular or elliptic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82104 using screen printing
• CPC Class Codes: H01L 2224/8284 Sintering
• CPC Class Codes: H01L 2224/83011 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/83085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/83194 Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/83815 Reflow soldering
• CPC Class Codes: H01L 2224/92224 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Abstract

An emissive panel and associated assembly method are provided. The method provides an emissive substrate having an insulating layer with a top surface and a back surface, and a dielectric layer overlying the insulating layer patterned to form a plurality of wells. Each well has a bottom surface formed on the insulating layer top surface with a first electrical interface electrically connected to a first conductive pressure channel (CPC). The CPCs are each made up of a pressure via with sidewalls formed between the well bottom surface and the insulating layer back surface. A metal layer coats the sidewalls, and a medium flow passage formed interior to the metal layer. The method uses negative pressure through the CPCs to help capture emissive elements in a liquid flow deposition process.

Claims

1. A fluidic assembly method for the fabrication of emissive panels, the method comprising:

providing an emissive substrate comprising an insulating layer with a top surface and a back surface, a dielectric layer overlying the insulating layer top surface patterned to form a plurality of wells, each well comprising a bottom surface formed on the insulating layer top surface with a first electrical interface electrically connected to a first conductive pressure channel, which is operatively connected to a conductive first matrix trace, the emissive substrate further comprising a conductive second matrix of traces, where first matrix traces are formed on a surface selected from the surface group consisting of the insulating layer top surface and the insulating layer bottom surface, and wherein the second matrix traces are formed on the unselected surface;

flowing a liquid suspension of emissive elements across the dielectric layer;

applying a negative pressure, from the insulating layer back surface to the wells, via the first conductive pressure channels;

capturing the emissive elements in the wells;

annealing the emissive substrate; and

,

in response to the annealing, electrically connecting a first electrical contact of each emissive element to the first electrical interface of a corresponding well.

2. The method of claim 1 wherein providing the emissive substrate includes each well bottom surface additionally comprising a second electrical interface electrically connected to a second conductive pressure channel formed between the insulating layer top and back surfaces, and with the second matrix traces operatively connected to corresponding second conductive pressure channels;

wherein flowing the liquid suspension of emission elements includes flowing emissive elements having a top surface with the first electrical contact and a second electrical contact; and

,

wherein electrically connecting the first electrical contact of each emissive element to the first electrical interface of a corresponding well in response to the annealing additionally includes electrically connecting the second electrical contact of each emissive element to the second electrical interface of a corresponding well.

3. The method of claim 1 wherein providing the emissive substrate includes the first matrix traces being formed on the insulating layer bottom surface, and each well bottom surface additionally comprising a second electrical interface electrically connected by a conductive intralevel trace, formed on the insulating layer top surface to a corresponding second matrix trace;

wherein flowing the liquid suspension of emission elements includes flowing emissive elements having a top surface with the first electrical contact and a second electrical contact; and

,

wherein electrically connecting the first electrical contact of each emissive element to the first electrical interface of a corresponding well in response to the annealing additionally includes electrically connecting the second electrical contact of each emissive element to the second electrical interface of a corresponding well.

4. The method of claim 1 wherein each conductive pressure channel comprises:

a pressure via with sidewalls formed between the well bottom surface and the insulating layer back surface;

a metal layer coating the sidewalls; and

,

a medium flow passage formed interior to the metal layer.

5. The method of claim 4 wherein each pressure via has a minimum cross-sectional area;

and,

wherein the medium flow passage has a minimum cross-sectional area greater than 50% of the pressure via minimum cross-sectional area.

6. The method of claim 1 wherein capturing the emissive elements in the wells includes capturing the emissive elements in response to the combination of the negative pressure and the suspension flow.

7. The method of claim 1 wherein flowing the liquid suspension across the emissive substrate top surface includes engaging an auxiliary mechanism for distributing the emissive elements selected from the group consisting of a brush (rotating or non-rotating), wiper, rotating cylinder, and mechanical vibration.

8. The method of claim 1 further comprising:

prior to annealing the emissive substrate, introducing a solder flux to each first electrical interface through a corresponding first conductive pressure channel.

9. The method of claim 1 wherein applying the negative pressure includes using a process selected from the group consisting of:

locating the insulating layer back surface overlying a porous support substrate and applying the negative pressure through the support substrate;

or,

attaching the emissive substrate to a frame perimeter with a center opening, and applying the negative pressure through the frame opening.

10. The method of claim 1 wherein providing the emissive substrate includes:

providing the insulating layer;

forming an array of pressure vias from the insulating layer top surface to the insulating layer back surface;

depositing metal overlying the insulating layer top surface, insulating layer back surface, and pressure vias, wherein the pressure vias are coated with metal, leaving a medium flow passage;

patterning the insulating layer top surface metal layer to expose well bottom surfaces and form the second matrix of traces, and patterning the insulating layer back surface to form the first matrix of traces; and

,

forming the patterned dielectric layer overlying the insulating layer top surface exposing the well bottom surfaces.

11. The method of claim 1 wherein providing the emissive substrate includes:

providing the insulating layer;

forming an array of pressure vias from the insulating layer top surface to the insulating layer back surface;

forming a photo-sensitive material overlying the insulating layer top surface and back surface, patterned to expose the pressure vias, first matrix trace regions, and second matrix trace regions;

depositing metal overlying the insulating layer top surface, insulating layer back surface, and pressure vias, wherein the pressure vias are coated with metal, leaving a medium flow passage; and

,

forming the patterned dielectric layer overlying the insulating layer top surface exposing the well bottom surfaces.

12. The method of claim 1 wherein providing the emissive substrate includes the first matrix traces being formed on the insulating layer bottom surface, and the dielectric layer having an intersection via associated with each well, exposing a corresponding second matrix trace;

wherein flowing the liquid suspension of emissive elements includes flowing vertical emissive elements having a top surface with the first electrical contact and a bottom surface with a second electrical contact; and

,

the method further comprising;

subsequent to annealing the emissive substrate, forming a local interconnect from the second electrical contact of each emissive element to the corresponding second matrix trace on the insulating layer top surface through a corresponding intersection via.

13. The method of claim 1 wherein flowing the liquid suspension of emission elements includes flowing emissive elements having a post connected to, and extending from the bottom surface.

14. The method of claim 1 further comprising:

subsequent to electrically connecting the first electrical contacts to the first electrical interfaces, forming a color modifier overlying the emissive elements.

15. The method of claim 14 further comprising:

subsequent to forming the color modifier, forming a liquid crystal display (LCD) panel overlying a top surface of the color modifier.

16. The method of claim 1 further comprising:

removing solvent from the liquid suspension and drying the emissive substrate in response to negative pressure applied through the first conductive channel.

17. An emissive panel comprising:

an insulating layer comprising a top surface and a back surface;

a dielectric layer overlying the insulating layer top surface, patterned to form a first plurality of wells, each well comprising a bottom surface formed on an exposed region of the insulating layer top surface, well sidewalls formed in the dielectric layer, a first electrical interface formed on the well bottom surface, and a first conductive pressure channel formed between the first electrical interface and the insulating layer back surface;

a control matrix comprising a conductive first matrix of traces formed on a surface selected from the surface group consisting of the insulating layer top surface and the insulating layer bottom surface, and wherein the second matrix traces are formed on the unselected surface, where each first conductive pressure channel is operatively connected to the first matrix;

a first plurality of surface mount emissive elements populating the wells, each emissive element comprising;

a top surface overlying a corresponding well bottom surface;

a bottom surface; and

,

a first electrical contact formed on the emissive element top surface and connected to a corresponding well first electrical interface.

18. The emissive panel of claim 17 further comprising:

a second electrical interface formed on each well bottom surface;

a second conductive pressure channel formed between the second electrical interface and the insulating layer back surface, operatively connected to a corresponding second matrix trace; and

,

wherein each emissive element further comprises a second electrical contact formed on the emissive element top surface, connected to a corresponding well second electrical interface.

19. The emissive panel of claim 17 wherein each emissive element further comprises a post connected to, and extending from the emissive element bottom surface.

20. The emissive panel of claim 17 further comprising:

a second electrical interface formed on each well bottom surface;

intralevel traces connecting each second matrix trace to corresponding second electrical interfaces; and

,

wherein each emissive element further comprises a second electrical contact formed on the emissive element top surface, connected to a corresponding well second electrical interface.

21. The emissive panel of claim 17 wherein each conductive pressure channel comprises:

a pressure via with sidewalls formed between the well bottom surface and the insulating layer back surface;

a metal layer coating the sidewalls; and

,

a medium flow passage formed interior to the metal layer.

22. The emissive panel of claim 21 wherein each pressure via has a minimum cross-sectional area;

and,

wherein the medium flow passage has a minimum cross-sectional area greater than 50% of the pressure via minimum cross-sectional area.

23. The emissive panel of claim 17 further comprising:

solder flux residue residing on the emissive element top surfaces and in the first conductive pressure channels.

24. The emissive panel of claim 17 further comprising:

a color modifier overlying the emissive elements.

25. The emissive panel of claim 24 further comprising:

a liquid crystal display (LCD) panel overlying a top surface of the color modifier.

26. The emissive panel of claim 17 wherein each emission element is a vertical emissive element further comprising a second electrical contact formed on the vertical emissive element bottom surface;

wherein the dielectric layer further comprises an intersection via associated with each well, exposing a corresponding second matrix trace; and

,

the emissive panel further comprising;

a plurality of conductive local interconnects overlying the dielectric layer, each local interconnect connecting a vertical emissive element second electrical contact to a second matrix trace through a corresponding column intersection via.