INTERCONNECT STRUCTURES FOR ASSEMBLY OF SEMICONDUCTOR STRUCTURES INCLUDING SUPERCONDUCTING INTEGRATED CIRCUITS

• US 20180012932A1
• Filed: 11/03/2016
• Published: 01/11/2018
• Est. Priority Date: 11/05/2015
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Oliver, William D., Kerman, Andrew J., Das, Rabindra N., Yost, Donna-Ruth W., Rosenberg, Danna, Gouker, Mark A.
• Granted Patent: US 10,396,269 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02345 treatment by exposure to radiation, e.g. visible light
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/11001 Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/11005 for aligning the bump connector, e.g. marks, spacers
• CPC Class Codes: H01L 2224/1111 Shaping
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11474 : Multilayer masks
• CPC Class Codes: H01L 2224/117 : involving monitoring, e.g. feedback loop
• CPC Class Codes: H01L 2224/11902 : Multiple masking steps
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/8181 : involving forming an intermetallic compound at the bonding interface
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H10N 60/12 : Josephson-effect devices
• CPC Class Codes: H10N 60/80 : Constructional details
• CPC Class Codes: H10N 60/805 : for Josephson-effect devices
• CPC Class Codes: H10N 60/81 : Containers; Mountings
• CPC Class Codes: H10N 69/00 : Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Abstract

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Claims

1. A multi-layer semiconductor structure, comprising:

a first semiconductor structure having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces;

a second semiconductor structure having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces, wherein at least one of the first and second semiconductor structures is a superconducting semiconductor structure; and

one or more interconnect structures, each of the interconnect structures disposed between the first and second semiconductor structures and coupled to respective ones of the interconnect pads provided on the first and second semiconductor structures, and each of the interconnect structures including a plurality of interconnect sections, wherein at least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

2. The multi-layer semiconductor structure of claim 1 wherein each of the interconnect sections includes one or more electrically conductive materials, and each of interconnect sections has a different, respective melting point than other ones of the interconnect sections.

3. The multi-layer semiconductor structure of claim 1 wherein each of the interconnect structures has first and second opposing portions and includes:

a first interconnect section having first and second opposing portions, wherein the first portion of the first interconnect section corresponds to the first portion of the interconnect structure;

a second interconnect section having first and second opposing portions, wherein the first portion of the second interconnect section is disposed over the second portion of the first interconnect section; and

a third interconnect section having first and second opposing portions, wherein the first portion of the third interconnect section is disposed over the second portion of the second interconnect section, and the second portion of the third interconnect section corresponds to the second portion of the interconnect structure.

4. The multi-layer semiconductor structure of claim 3 wherein the first interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials.

5. The multi-layer semiconductor structure of claim 4 wherein each of the conductive layers has a different, respective melting point.

6. The multi-layer semiconductor structure of claim 4 wherein a first one of the conductive layers includes Titanium (Ti) and/or Lead (Pb), a second one of the conductive layers includes Platinum (Pt) and/or Tin (Sn), and a third one of the conductive layers includes Gold (Au) and/or Indium (In).

7. The multi-layer semiconductor structure of claim 4 wherein the third interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials.

8. The multi-layer semiconductor structure of claim 3 wherein the first interconnect section and the third interconnect section are both provided as under bump metals (UBMs).

9. The multi-layer semiconductor structure of claim 8 wherein the second interconnect section is provided as a solder ball, sphere, pillar or micro-bump.

10. The multi-layer semiconductor structure of claim 1, wherein the first semiconductor has a first package pitch and the second semiconductor structure has a second package pitch, and one or more characteristics of the interconnect structures are selected based upon at least one of the first package pitch and the second package pitch.

11. The multi-layer semiconductor structure of claim 10 wherein the one or more characteristics include dimensions of the interconnect structures and materials of the interconnect structures.

12. The multi-layer semiconductor structure of claim 1 wherein the interconnect structures form a micro bump assembly on at least one of the first and second semiconductor structures.

13. The multi-layer semiconductor structure of claim 1 wherein the first semiconductor structure is a multi-chip module (MCM) or an interposer module.

14. The multi-layer semiconductor structure of claim 1 wherein the second semiconductor structure includes a qubit.

15. The multi-layer semiconductor structure of claim 1 wherein the second semiconductor structure is a superconducting semiconductor structure and is designed to operate in at least one of a radio frequency (RF) region and a microwave frequency region.

16. An interconnect structure for coupling two or more semiconductor structures together, wherein at least one of the semiconductor structures is a superconducting semiconductor structure, the interconnect structure having first and second opposing portions and comprising:

a first interconnect section having first and second opposing portions, wherein the first portion of the first interconnect section corresponds to the first portion of the interconnect structure;

a second interconnect section having first and second opposing portions, wherein the first portion of the second interconnect section is disposed over the second portion of the first interconnect section; and

a third interconnect section having first and second opposing portions, wherein the first portion of the third interconnect section is disposed over the second portion of the second interconnect section, and wherein at least one of the first, second and third interconnect sections comprises a superconducting and/or a partially superconducting material.

17. The interconnect structure of claim 16 wherein the first interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials.

18. The interconnect structure of claim 17 wherein each of the conductive layers has a different, respective melting point.

19. The interconnect structure of claim 17 wherein the third interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials.

20. The interconnect structure of claim 16 wherein the first interconnect section and the third interconnect section are both provided as under bump metals (UBMs).