RESISTIVE MEMORY CELL HAVING A COMPACT STRUCTURE
First Claim
1. A memory cell comprising:
- a selection transistor having a control gate and a first conduction terminal;
a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includes;
a semiconductor substrate,a first insulating layer covering the semiconductor substrate, anda semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,a second insulating layer covering the lateral flank of the control gate,a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, anda trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer.
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Abstract
The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
2 Citations
19 Claims
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1. A memory cell comprising:
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a selection transistor having a control gate and a first conduction terminal; a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includes; a semiconductor substrate, a first insulating layer covering the semiconductor substrate, and a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank, a second insulating layer covering the lateral flank of the control gate, a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, and a trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory, comprising:
a first memory cell that includes; a first selection transistor having a control gate and first and second conduction terminals, the first and second conduction terminals being positioned in a semiconductor layer; a first insulating layer having a first portion on a lateral sidewall of the control gate and having a second portion on a top of the control gate; and a first variable-resistance element being on the first and second portions of the first insulating layer and extending into the semiconductor layer, the first insulating layer electrically insulating the control gate from the variable-resistance element. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A process for fabricating an integrated circuit having a memory cell, the process comprising:
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forming a selection transistor of the memory cell on a semiconductor substrate covered with a first insulating layer, the first insulating layer being covered with a semiconductive active layer, the selection transistor including a control gate and first and second conduction terminals; covering with a second insulating layer a lateral flank of the control gate on a same side as the first conduction terminal; producing a first trench through the active layer in the first conduction terminal, reaching the first insulating layer; depositing a layer of a variable-resistance material in the first trench, covering a lateral flank of the active layer in the first trench; and forming in the layer of variable-resistance material a trench conductor reaching the first insulating layer. - View Dependent Claims (17, 18, 19)
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Specification