TRENCH-BASED POWER SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGE CHARACTERISTICS

• US 20180012958A1
• Filed: 08/28/2017
• Published: 01/11/2018
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: YEDINAK, Joseph A., CHALLA, Ashok, PROBST, Dean E., KINZER, Daniel
• Granted Patent: US 10,868,113 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device comprising:

a plurality of primary trenches extending into the semiconductor region, each of the plurality of trenches having a first end, a second end, and opposing sidewalls lined with a dielectric layer, each trench further having a shield electrode;

an end trench extending into the semiconductor region and disposed adjacent to and spaced from the first ends of the primary trenches, the end trench having opposing sidewalls lined with a dielectric layer and an electrode disposed in the end trench; and

a gap region disposed between the end trench and the first ends of the primary trenches, the gap region being at a floating potential.

2. The semiconductor device of claim 1, wherein the electrode disposed in the end trench is electrically coupled to a conductive layer to receive a potential.

3. The semiconductor device of claim 2, a well region of a first conductivity type disposed in the semiconductor region and in the gap region, the well being at a floating potential.

4. The semiconductor device of claim 1, wherein the electrode disposed in the end trench is at a floating potential.

5. The semiconductor device of claim 4, a well region of a first conductivity type disposed in the semiconductor region and in the gap region, the well being at a floating potential.

6. The semiconductor device of claim 1, wherein the end trench fully encircle the plurality of primary trenches.

7. The semiconductor device of claim 1, wherein each primary trench further has a gate electrode vertically stacked on the shield electrode, the gate and shield electrodes being insulated from each other.