FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE
First Claim
1. A method of forming a vertical fin field effect transistor (vertical finFET) with a reduced source/drain contact resistance, comprising:
- forming a doped region on a substrate;
forming a plurality of vertical fins on the doped region;
heat treating the doped region and the plurality of vertical fins to diffuse dopant from the doped region into a lower portion of each of the plurality of vertical fins; and
removing an upper portion of at least one of the plurality of vertical fins and leaving at least one of the plurality of vertical fins on the doped region, wherein the lower portion of the at least one of the plurality of vertical fins remains as a doped extension on the doped region, wherein the at least one doped extension is electrically coupled with the doped region, and the at least one doped extension increases the surface area of the doped region.
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Accused Products
Abstract
A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.
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Citations
20 Claims
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1. A method of forming a vertical fin field effect transistor (vertical finFET) with a reduced source/drain contact resistance, comprising:
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forming a doped region on a substrate; forming a plurality of vertical fins on the doped region; heat treating the doped region and the plurality of vertical fins to diffuse dopant from the doped region into a lower portion of each of the plurality of vertical fins; and removing an upper portion of at least one of the plurality of vertical fins and leaving at least one of the plurality of vertical fins on the doped region, wherein the lower portion of the at least one of the plurality of vertical fins remains as a doped extension on the doped region, wherein the at least one doped extension is electrically coupled with the doped region, and the at least one doped extension increases the surface area of the doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:
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forming the doped region on a substrate, wherein the doped region has one or more interfacial features that increases the surface area of the doped region; forming the bottom source/drain contact on at least a portion of the doped region including the one or more interfacial features. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:
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forming a doped region on a substrate forming one or more doped extensions that extend outward from the top surface of the doped region; forming a bottom source/drain contact on at least a portion of the doped region including the one or more doped extensions. - View Dependent Claims (18, 19, 20)
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Specification