Qubit and Coupler Circuit Structures and Coupling Techniques

• US 20180013052A1
• Filed: 11/03/2016
• Published: 01/11/2018
• Est. Priority Date: 07/23/2015
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Oliver, William D., Kerman, Andrew J., Das, Rabindra N., Yost, Donna-Ruth W., Rosenberg, Danna, Gouker, Mark A.
• Granted Patent: US 10,134,972 B2
• Time in Patent Office: Days
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53285 containing superconducting materials
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H10N 60/12 Josephson-effect devices
• CPC Class Codes: H10N 60/805 for Josephson-effect devices
• CPC Class Codes: H10N 69/00 Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Abstract

Quantum bit (qubit) circuits, coupler circuit structures and coupling techniques are described. Such circuits and techniques may be used to provide multi-qubit circuits suitable for use in multichip modules (MCMs).

Claims

1. A cryogenic quantum bit package comprising:

(a) one or more quantum bit (qubit) integrated circuits, each of said one or more qubit integrated circuits comprising at least two qubit circuits;

(b) a quantum bit bias control line;

(c) a coupler circuit disposed to couple signals between said at least two qubit circuits;

(d) a superconducting multi-chip module (MCM); and

(e) one or more superconducting and/or nearly superconducting interconnects, each of said one or more superconducting interconnects disposed between and electrically coupled to said one or more quantum bit integrated circuits and said superconducting MCM such that a signal path is provided between said one or more qubit integrated circuits and said MCM.

2. The cryogenic quantum bit package of claim 1 wherein said coupler circuit comprises at least one of:

a Josephson junction;

a capacitive coupling circuit;

an inductive coupling circuit;

a resonator;

a qubit loop; and

a coupler loop.

3. The cryogenic quantum bit package of claim 1 wherein at least a portion of said at least two qubit circuits is disposed in said superconducting multi-chip module.

4. The cryogenic quantum bit package of claim 1 wherein at least a portion of said coupler circuit is disposed in said superconducting multi-chip module.

5. The cryogenic quantum bit package of claim 1 wherein at least a portion of said at least two qubit circuit and at least a portion of said coupler circuit are disposed in said superconducting multi-chip module.

6. The cryogenic quantum bit package of claim 1 wherein at least a portion of said quantum bit bias control line is disposed in said qubit integrated circuit.

7. The cryogenic quantum bit package of claim 1 wherein at least a portion of said quantum bit bias control line is disposed in said superconducting multi-chip module.

8. The cryogenic quantum bit package of claim 1 wherein at least one of said qubit integrated circuits and said superconducting MCM further comprises a bias control system configured to apply a local effective bias to a corresponding quantum device.

9. The cryogenic quantum bit package of claim 1 wherein said coupler circuit is disposed so as to provide coupling to a nearest-neighbor qubit circuit.

10. The cryogenic quantum bit package of claim 1 further comprising a plurality of couplers, each of said plurality of couplers disposed to couple to next nearest-neighbor qubit circuits.

11. The cryogenic quantum bit package of claim 10 wherein each of said qubit integrated circuits further comprises a coupling control system configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a desired coupling value.

12. A cryogenic quantum bit package comprising:

a first quantum bit (qubit) integrated circuit;

a second quantum bit integrated circuit;

a superconducting multi-chip-module (MOM);

an interposer disposed between said first and second quantum bit integrated circuits and said superconducting MCM, said interposer comprising a TSV substrate and disposed to electrically interconnect said first and second quantum bit integrated circuits to said superconducting MCM sandwich.

13. The cryogenic quantum bit package of claim 12 wherein said TSV interposer substrate having an opening provided therein and wherein the cryogenic quantum bit package further comprises at least one electrical component disposed in the opening of said TSV interposer substrate with said at least one electrical component electrically and mechanically coupled to said MCM.

14. The cryogenic quantum bit package of claim 12 wherein said MCM comprises one of:

a CMOS chip;

a qubit chip or an SFQ chip.

15. The cryogenic quantum bit package of claim 14 further comprising a third qubit chip disposed on an upper surface of said TSV substrate with the first and second qubit chips disposed in a first plane and said third qubit chip disposed in a second different plane and wherein said third qubit chip is disposed to couple signals between at least one of the first and second qubit integrated circuits disposed in the first plane.

16. The cryogenic quantum bit package of claim 15 wherein said first, second and third qubit chips are disposed to inductively couple signals therebetween.

17. The cryogenic quantum bit package of claim 16 wherein at least one of said qubit chips comprises a quantum bit circuit comprising:

a substrate having first and second opposing surfaces;

a conductive layer having first and second opposing surfaces, wherein the first surface of the conductive layer is disposed over the second surface of the substrate, and the conductive layer includes at least one conductive material, the at least one conductive material including a substantially low stress polycrystalline titanium nitride (TiN) material having an internal stress below about two hundred fifty megapascal (MPa), such that a superconducting resonator provided in the cryogenic quantum bit package and/or at least one of the qubit integrated circuits is provided as a substantially high quality factor, low loss superconducting resonator and/or qubit.

18. The cryogenic quantum bit package of claim 17 wherein the TiN material is a (200)-oriented polycrystalline.

19. The cryogenic quantum bit package of claim 18 wherein the TiN material is provided as a (200) oriented single crystal material having a 4-fold symmetry and in-plane rotational alignment.

20. The cryogenic quantum bit package of claim 17 wherein the substrate is provided from at least one of:

silicon;

deposited Silicon;

silicon having at least one surface with a high resistivity characteristic;

oxide coated silicon;

oxide etched silicon;

oxide etched annealed silicon;

glass;

aluminum oxide;

sapphire;

germanium;

gallium arsenide;

an alloy of silicon and germanium; and

indium phosphide.

21. The cryogenic quantum bit package of claim 20 wherein:

the substrate is at least one of a superconducting substrate or a partially superconducting substrate; and

the conductive layer comprises a superconducting bump and/or a partially superconducting bump disposed to electrically couple at least two qubit chips.