Clock Adjustment For Voltage Droop
First Claim
1. A method comprising:
- in response to detecting a voltage drop at a processor, modifying a first set of enable signals to generate a modified first set of enable signals; and
generating a first clock signal based on the modified first set of enable signals.
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Accused Products
Abstract
A processor adjusts frequencies of one or more clock signals in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals, each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.
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Citations
20 Claims
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1. A method comprising:
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in response to detecting a voltage drop at a processor, modifying a first set of enable signals to generate a modified first set of enable signals; and generating a first clock signal based on the modified first set of enable signals. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising generating a first set of enable signals;
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generating a first clock signal at a first frequency based on the first set of enable signals; providing the first clock signal at the first frequency to a processor; and in response to detecting a voltage drop at the processor, modifying the first set of enable signals to change a frequency of the first clock signal from the first frequency to a second frequency, the second frequency different from the first frequency. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A processor comprising:
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a voltage detection module to detect a voltage drop at the processor; a first clock module to receive a first set of enable signals and a first plurality of clock signals, the first clock module to generate a first clock signal based on the first set of enable signals and the plurality of clock signals; and a stretch control module to modify the first set of enable signals in response to the voltage detection module indicating the voltage drop. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification