MEMORY SYSTEM AND OPERATION METHOD FOR THE SAME

• US 20180018091A1
• Filed: 03/16/2017
• Published: 01/18/2018
• Est. Priority Date: 07/18/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SHIN, Woong-Sik, JEON, Jeong-Ho
• Granted Patent: US 10,466,902 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A memory system includes a memory device including a plurality of memory arrays, each of which includes a plurality of memory blocks, and a controller suitable for setting super blocks each including respective memory blocks that belong to two or more memory arrays among the plurality of the memory arrays and performing a garbage collection operation on the super blocks based on a valid page information and a wearing level of each super block.

Claims

1. A memory system, comprising:

a memory device including a plurality of memory arrays, each of which includes a plurality of memory blocks; and

a controller suitable for setting super blocks each including respective memory blocks that belong to two or more memory arrays among the plurality of the memory arrays and performing a garbage collection operation on the super blocks based on a valid page information and a wearing level of each super block.

2. The memory system of claim 1, wherein the valid page information of each super block includes the number of valid pages and the wearing level of each super block is based on the number of bad blocks included in the super blocks, respectively.

3. The memory system of claim 2, wherein the controller performs the garbage collection operation on the super blocks by counting pages of the bad blocks as valid pages.

4. The memory system of claim 2, wherein the controller performs the garbage collection operation by assigning a weight to the number of the bad blocks to produce a weighted number of the bad blocks, adding the number of the valid pages to the weighted number of the bad blocks, and selecting a super block having a smallest value among the added results as a victim block.

5. The memory system of claim 4, wherein the weight represents the total number of pages that are included in each of the bad blocks.

6. The memory system of claim 4, wherein the controller disables a super block that includes bad blocks more than a threshold number based on the number of the bad blocks.

7. The memory system of claim 6, wherein the controller adjusts the weight based on the threshold number.

8. The memory system of claim 1, wherein the controller simultaneously erases data of memory blocks included in each of the super blocks, and simultaneously writes data in respective pages of the memory blocks or simultaneously reads data from the respective pages.

9. The memory system of claim 1, wherein each of the super blocks includes memory blocks that are positioned at the same physical block positions in the more than two different memory arrays.

10. The memory system of claim 1, wherein the plurality of the memory arrays correspond to memory dies that are included in different memory chips.

11. A memory system, comprising:

a memory device including a plurality of memory arrays, each of which includes a plurality of memory blocks; and

a controller suitable for generating valid page information and bad block information for super blocks, each of which includes respective memory blocks that belong to two or more memory arrays among the plurality of the memory arrays, and determining reference values that are used for selecting a victim block for a garbage collection operation among the super blocks based on the valid page information and the bad block information.

12. The memory system of claim 11, wherein the controller generates the valid page information and the bad block information by counting the number of valid pages and the number of bad blocks that are included in the super blocks, respectively.

13. The memory system of claim 12, wherein the controller determines the reference values by assigning a weight to the counted number of the bad blocks so as to produce a weighted number of the bad blocks, and adding the counted number of the valid pages to the weighted number of the bad blocks.

14. The memory system of claim 13, wherein the weight represents the total number of pages that are included in each of the bad blocks.

15. The memory system of claim 11, wherein the controller determines an empty space of the memory device, and when the empty space is smaller than a threshold value, the controller compares the reference values, selects a super block having a smallest reference value among the reference values as the victim block, and performs the garbage collection operation on the victim block.

16. The memory system of claim 15, wherein the controller determines the empty space of the memory device by counting the number of free memory blocks that are available for storing new data in the memory device.

17. The memory system of claim 15, wherein the controller performs the garbage collection operation by copying and storing data that are stored in valid pages of the victim block into free memory blocks in the memory device and erasing data that are stored in the victim block.

18. The memory system of claim 11, wherein the controller reads data from the memory blocks, detects an error that occurs in the read data, and decides bad blocks based on the detected error.

19. A method for operating a memory system, comprising:

generating valid page information and bad block information of super blocks, each of which includes respective memory blocks that belong to different memory arrays;

determining reference values that are used for selecting a victim block for a garbage collection operation among the super blocks based on the valid page information and the bad block information; and

performing the garbage collection operation on the super blocks based on the reference values.

20. The method of claim 19, wherein the generating of the valid page information and the bad block information of the super blocks includes counting the number of valid pages and the number of bad blocks that are included in the super blocks, respectively, and

wherein the determining of the reference values includes:

assigning a weight to the counted number of the bad blocks so as to produce a weighted number of the bad blocks; and

determining the reference values by adding the counted number of the valid pages to the weighted number of the bad blocks.