ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE, AND DISPLAY DEVICE

• US 20180019263A1
• Filed: 04/15/2016
• Published: 01/18/2018
• Est. Priority Date: 06/05/2015
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: KONG, Xiangyong, CHENG, Jun, LIU, Xiaodi
• Granted Patent: US 10,186,527 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The embodiments of present disclosure disclose an array substrate, a method for manufacturing the array substrate, and a display device. The method includes forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.

Claims

1. A method for manufacturing an array substrate, the method comprising:

forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, and the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and wherein a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.

2. The method according to claim 1, wherein the method further comprises forming a conductive buffer layer between the pixel electrode layer and the gate metal layer.

3. The method according to claim 2, wherein the method further comprises:

forming a photoresist layer on the gate metal layer;

forming a fully exposed area, an unexposed area, and a grayscale exposed area in the photoresist layer using a grayscale mask plate through an exposure-and-development process to remove photoresist of the fully exposed area and partial photoresist of the grayscale exposed area;

etching the pixel electrode layer, the conductive buffer layer, and the gate metal layer located below the fully exposed area;

removing the photoresist of the grayscale exposed area using the grayscale mask plate;

etching the conductive buffer layer and the gate metal layer located below the grayscale exposed area to form a pixel electrode pattern and the first connection part pattern; and

removing the photoresist of the unexposed area to form a gate pattern and the second connection part pattern.

4. The method according to claim 2, wherein a material of the conductive buffer layer includes one of a molybdenum-niobium alloy and titanium.

5. The method according to claim 1, wherein a material of both the gate metal layer and the source/drain metal layer includes copper.

6. The method according to claim 1, wherein the method further comprises:

forming a gate insulating layer and an etching barrier layer; and

forming, at a portion of the gate insulating layer and the etching barrier layer where an electric connection between the first connection part pattern and the third connection part pattern are to be formed, a first via hole for electrically connecting the first connection part pattern with the third connection part pattern.

7. The method according to claim 6, wherein one of a source pattern and a drain pattern disposed in the source/drain metal layer is electrically connected with a pixel electrode pattern disposed in the pixel electrode layer through a second via hole penetrating through the etching barrier layer and the gate insulating layer.

15. The method according to claim 3, wherein a material of the conductive buffer layer includes one of a molybdenum-niobium alloy and titanium.

8. An array substrate comprising:

a base substrate, a pixel electrode layer, a gate metal layer and a source/drain metal layer, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, and the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and wherein a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.

9. The array substrate according to claim 8, wherein the array substrate further comprises an etching barrier layer and a gate insulating layer disposed between the pixel electrode layer and the source/drain metal layer, the first via hole penetrating through the etching barrier layer and the gate insulating layer.

10. The array substrate according to claim 8, wherein the array substrate further comprises a conductive buffer layer disposed between the pixel electrode layer and the gate metal layer.

11. The array substrate according to claim 10, wherein a material of the conductive buffer layer includes one of a molybdenum-niobium alloy and titanium.

12. The array substrate according to claim 9, wherein one of a source pattern and a drain pattern disposed in the source/drain metal layer is electrically connected with a pixel electrode pattern disposed in the pixel electrode layer through a second via hole penetrating through the etching barrier layer and the gate insulating layer.

13. The array substrate according to claim 8, wherein a material of both the gate metal layer and the source/drain metal layer includes copper.

14. A display device comprising the array substrate according to claim 8.

16. The array substrate according to claim 9, wherein the array substrate further comprises a conductive buffer layer disposed between the pixel electrode layer and the gate metal layer.

17. A display device comprising the array substrate according to claim 9.

18. A display device comprising the array substrate according to claim 10.

19. A display device comprising the array substrate according to claim 11.

20. A display device comprising the array substrate according to claim 12.