ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE, AND DISPLAY DEVICE
First Claim
1. A method for manufacturing an array substrate, the method comprising:
- forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, and the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and wherein a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.
1 Assignment
0 Petitions
Accused Products
Abstract
The embodiments of present disclosure disclose an array substrate, a method for manufacturing the array substrate, and a display device. The method includes forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.
-
Citations
20 Claims
-
1. A method for manufacturing an array substrate, the method comprising:
- forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, and the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and wherein a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 15)
-
8. An array substrate comprising:
- a base substrate, a pixel electrode layer, a gate metal layer and a source/drain metal layer, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, and the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and wherein a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.
- View Dependent Claims (9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20)
Specification